[llvm] f113cab - [AMDGPU] Cleanup bytesel variables. NFC. (#140131)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 15 16:04:28 PDT 2025
Author: Stanislav Mekhanoshin
Date: 2025-05-15T16:04:24-07:00
New Revision: f113cab1912c19581a48b7330cadfbd24f51fc58
URL: https://github.com/llvm/llvm-project/commit/f113cab1912c19581a48b7330cadfbd24f51fc58
DIFF: https://github.com/llvm/llvm-project/commit/f113cab1912c19581a48b7330cadfbd24f51fc58.diff
LOG: [AMDGPU] Cleanup bytesel variables. NFC. (#140131)
Somehow we ended up with 2 sets of td variables: Is...ByteSel and
Has...ByteSel. Keep only Has... form.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/VOP1Instructions.td
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/lib/Target/AMDGPU/VOPInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 6993095193467..47ee0a7f60ee3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2539,11 +2539,10 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
field bit IsWMMA = 0;
field bit IsSWMMAC = 0;
- field bit IsFP8SrcByteSel = 0;
- field bit IsFP8DstByteSel = 0;
+ field bit HasFP8SrcByteSel = 0;
field bit HasFP8DstByteSel = 0;
field bit HasFP4DstByteSel = 0;
- field bit IsFP8ByteSel = !or(IsFP8SrcByteSel, IsFP8DstByteSel);
+ field bit HasFP8ByteSel = !or(HasFP8SrcByteSel, HasFP8DstByteSel);
field bit HasDst = !ne(DstVT.Value, untyped.Value);
field bit HasDst32 = HasDst;
@@ -2660,7 +2659,7 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
field string AsmDPP8 = getAsmDPP8<HasDst, NumSrcArgs, 0 /*HasModifiers*/, DstVT>.ret;
field string AsmVOP3Base = getAsmVOP3Base<NumSrcArgs, HasDst, HasClamp,
HasOpSel, HasOMod, IsVOP3P, HasNeg, HasModifiers, HasModifiers,
- HasModifiers, DstVT, IsFP8ByteSel>.ret;
+ HasModifiers, DstVT, HasFP8ByteSel>.ret;
field string Asm64 = AsmVOP3Base;
field string AsmVOP3P = getAsmVOP3P<HasDst, NumSrcArgs, HasNeg, HasClamp, HasOpSel>.ret;
field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs,
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 073c45ff6fa99..f885de3c13b12 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -666,7 +666,7 @@ let HasClamp = 0, HasOMod = 0, HasExtDPP = 0, HasExtVOP3DPP = 0,
}
class VOPProfile_Base_CVT_F_F8_ByteSel<ValueType DstVT> : VOPProfile<[DstVT, i32, untyped, untyped]> {
- let IsFP8SrcByteSel = 1;
+ let HasFP8SrcByteSel = 1;
let HasOpSel = 0;
let HasExtDPP = 1;
let HasExtVOP3DPP = 1;
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 73f7a5cccaa07..a7b90b9e319da 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -605,7 +605,6 @@ def VOP3_CVT_SR_F8_F32_Profile : VOP3_Profile<VOPProfile<[i32, f32, i32, f32]>,
class VOP3_CVT_SR_F8_ByteSel_Profile<ValueType SrcVT> :
VOP3_Profile<VOPProfile<[i32, SrcVT, i32, untyped]>> {
- let IsFP8DstByteSel = 1;
let HasFP8DstByteSel = 1;
let HasClamp = 0;
defvar bytesel = (ins VGPR_32:$vdst_in, ByteSel:$byte_sel);
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index f9fa83c3f5ae7..24032353a00e9 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -869,13 +869,13 @@ class VOP3_DPPe_Common_Base<bits<10> op, VOPProfile P> : Enc96 {
let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0);
// 16-bit select fields which can be interpreted as OpSel or hi/lo suffix
let Inst{11} = !if(P.HasOpSel, !if(P.HasSrc0Mods, src0_modifiers{2}, 0),
- !if(P.IsFP8SrcByteSel, byte_sel{1}, ?));
+ !if(P.HasFP8SrcByteSel, byte_sel{1}, ?));
let Inst{12} = !if(P.HasOpSel, !if(P.HasSrc1Mods, src1_modifiers{2}, 0),
- !if(P.IsFP8SrcByteSel, byte_sel{0}, ?));
+ !if(P.HasFP8SrcByteSel, byte_sel{0}, ?));
let Inst{13} = !if(P.HasOpSel, !if(P.HasSrc2Mods, src2_modifiers{2}, 0),
- !if(P.IsFP8DstByteSel, byte_sel{0}, ?));
+ !if(P.HasFP8DstByteSel, byte_sel{0}, ?));
let Inst{14} = !if(P.HasOpSel, !if(P.HasSrc0Mods, src0_modifiers{3}, 0),
- !if(P.IsFP8DstByteSel, byte_sel{1}, ?));
+ !if(P.HasFP8DstByteSel, byte_sel{1}, ?));
let Inst{15} = !if(P.HasClamp, clamp, 0);
let Inst{25-16} = op;
let Inst{31-26} = 0x35;
@@ -1695,11 +1695,11 @@ multiclass VOP3_Real_Base<GFXGen Gen, bits<10> op, string opName = NAME,
bit isSingle = 0> {
defvar ps = !cast<VOP_Pseudo>(opName#"_e64");
let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
- if ps.Pfl.IsFP8SrcByteSel then {
+ if ps.Pfl.HasFP8SrcByteSel then {
def _e64#Gen.Suffix :
VOP3_Real_Gen<ps, Gen>,
VOP3FP8OpSel_src_bytesel_gfx11_gfx12<op, ps.Pfl>;
- } else if ps.Pfl.IsFP8DstByteSel then {
+ } else if ps.Pfl.HasFP8DstByteSel then {
def _e64#Gen.Suffix :
VOP3_Real_Gen<ps, Gen>,
VOP3FP8OpSel_dst_bytesel_gfx11_gfx12<op, ps.Pfl>;
@@ -1733,11 +1733,11 @@ multiclass VOP3_Real_with_name<GFXGen Gen, bits<10> op, string opName,
let AsmString = asmName # ps.AsmOperands,
IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
// FIXME-TRUE16 support FP8 instructions properly
- if ps.Pfl.IsFP8SrcByteSel then {
+ if ps.Pfl.HasFP8SrcByteSel then {
def _e64#Gen.Suffix :
VOP3_Real_Gen<ps, Gen>,
VOP3FP8OpSel_src_bytesel_gfx11_gfx12<op, ps.Pfl>;
- } else if ps.Pfl.IsFP8DstByteSel then {
+ } else if ps.Pfl.HasFP8DstByteSel then {
def _e64#Gen.Suffix :
VOP3_Real_Gen<ps, Gen>,
VOP3FP8OpSel_dst_bytesel_gfx11_gfx12<op, ps.Pfl>;
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