[llvm] [RISCV] Add Zilsd to RISCVMergeBaseOffset. (PR #140157)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/140157

I only tested a simple case for folding the addi from medany codemodel. I assume everything else should just work.

>From 2e996304cabc4b2ce035d98f85bce9cef821df39 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 15 May 2025 15:40:41 -0700
Subject: [PATCH 1/2] Pre-commit test

---
 .../RISCV/fold-addi-loadstore-zilsd.ll        | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll

diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
new file mode 100644
index 0000000000000..29f05c3be45c0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zilsd -verify-machineinstrs \
+; RUN:   -code-model=medium < %s | FileCheck %s
+
+ at g_0 = global double 0.0
+
+define double @load_g_0() nounwind {
+; CHECK-LABEL: load_g_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .Lpcrel_hi0:
+; CHECK-NEXT:    auipc a0, %pcrel_hi(g_0)
+; CHECK-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
+; CHECK-NEXT:    ld a0, 0(a0)
+; CHECK-NEXT:    ret
+entry:
+  %0 = load double, ptr @g_0
+  ret double %0
+}
+
+define void @store_g_0() nounwind {
+; CHECK-LABEL: store_g_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .Lpcrel_hi1:
+; CHECK-NEXT:    auipc a0, %pcrel_hi(g_0)
+; CHECK-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
+; CHECK-NEXT:    fcvt.d.w a2, zero
+; CHECK-NEXT:    sd a2, 0(a0)
+; CHECK-NEXT:    ret
+entry:
+  store double 0.0, ptr @g_0
+  ret void
+}

>From 436ca72cd11a3cf7b4b33e8d9ee238baf31ae369 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 15 May 2025 15:52:06 -0700
Subject: [PATCH 2/2] [RISCV] Add Zilsd to RISCVMergeBaseOffset.

---
 llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp       | 2 ++
 llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll | 6 ++----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
index eb3d43c9af7c2..60ebd0fdff2a8 100644
--- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -409,6 +409,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
     case RISCV::LHU:
     case RISCV::LWU:
     case RISCV::LD:
+    case RISCV::LD_RV32:
     case RISCV::FLH:
     case RISCV::FLW:
     case RISCV::FLD:
@@ -418,6 +419,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
     case RISCV::SW:
     case RISCV::SW_INX:
     case RISCV::SD:
+    case RISCV::SD_RV32:
     case RISCV::FSH:
     case RISCV::FSW:
     case RISCV::FSD: {
diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
index 29f05c3be45c0..e34c5272ebaeb 100644
--- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
@@ -9,8 +9,7 @@ define double @load_g_0() nounwind {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:  .Lpcrel_hi0:
 ; CHECK-NEXT:    auipc a0, %pcrel_hi(g_0)
-; CHECK-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
-; CHECK-NEXT:    ld a0, 0(a0)
+; CHECK-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
 ; CHECK-NEXT:    ret
 entry:
   %0 = load double, ptr @g_0
@@ -22,9 +21,8 @@ define void @store_g_0() nounwind {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:  .Lpcrel_hi1:
 ; CHECK-NEXT:    auipc a0, %pcrel_hi(g_0)
-; CHECK-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
 ; CHECK-NEXT:    fcvt.d.w a2, zero
-; CHECK-NEXT:    sd a2, 0(a0)
+; CHECK-NEXT:    sd a2, %pcrel_lo(.Lpcrel_hi1)(a0)
 ; CHECK-NEXT:    ret
 entry:
   store double 0.0, ptr @g_0