[llvm] [LLVM][TableGen] Simplify `DagInit::get` (PR #140056)

[Min-Yih Hsu via llvm-commits]

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@@ -213,8 +213,9 @@ void VarLenInst::buildRec(const DagInit *DI) {
     if (NeedSwap) {
       // Normalization: Hi bit should always be the second argument.
       const Init *const NewArgs[] = {OperandName, LoBit, HiBit};
-      Segments.push_back({NumBits,
-                          DagInit::get(DI->getOperator(), nullptr, NewArgs, {}),
+      // TODO: This creates an invalid DagInit with 3 Args but 0 ArgNames.
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mshockwave wrote:

oh I should fill in nullptr rather than not providing anything! thanks for catching this. You could fix it and I'll take a final look and see if we should just enforce the ordering like you suggested.

https://github.com/llvm/llvm-project/pull/140056