[llvm] 21d5064 - [X86] combineConcatVectorOps - remove VBMI2 limit for v32i16/v64i8 shuffle concatentation (#140077)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2025-05-15T17:20:53+01:00
New Revision: 21d506414053d260ee78fa5a27b6bf3edc547088

URL: https://github.com/llvm/llvm-project/commit/21d506414053d260ee78fa5a27b6bf3edc547088
DIFF: https://github.com/llvm/llvm-project/commit/21d506414053d260ee78fa5a27b6bf3edc547088.diff

LOG: [X86] combineConcatVectorOps - remove VBMI2 limit for v32i16/v64i8 shuffle concatentation (#140077)

This is no longer required with the improvements to subvector load sharing with shouldReduceLoadWidth

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8c6c987c552cc..9be3b39ce16fa 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58403,9 +58403,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
           ((VT.is256BitVector() &&
             (EltSizeInBits >= 32 || Subtarget.hasInt256())) ||
            (VT.is512BitVector() && Subtarget.useAVX512Regs() &&
-            (EltSizeInBits >= 32 || Subtarget.hasVBMI2())))) {
-        // TODO: Relax VBMI requirement for repeated shuffle ops - currently
-        // limited to targets that should always have good cross lane shuffles.
+            (EltSizeInBits >= 32 || Subtarget.useBWIRegs())))) {
         SDValue Concat0 = CombineSubOperand(VT, Ops, 0);
         SDValue Concat1 = CombineSubOperand(VT, Ops, 1);
         if (Concat0 || Concat1 ||