[llvm] 540cf25 - [RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 15 08:35:46 PDT 2025
Author: Craig Topper
Date: 2025-05-15T08:35:43-07:00
New Revision: 540cf25a6df56fa1810a7411477dca9896aeed20
URL: https://github.com/llvm/llvm-project/commit/540cf25a6df56fa1810a7411477dca9896aeed20
DIFF: https://github.com/llvm/llvm-project/commit/540cf25a6df56fa1810a7411477dca9896aeed20.diff
LOG: [RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
This avoids a bunch of complexity around making sure the offset doesn't
exceed 4093 so we can add 4 after splitting later. By splitting early,
the split loads/stores will get selected independently.
There's a bit of follow up work to do, particularly around splitting a
constant pool load. Overall I think this is cleaner with less edge
cases.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/test/CodeGen/RISCV/double-calling-conv.ll
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/double-imm.ll
llvm/test/CodeGen/RISCV/double-mem.ll
llvm/test/CodeGen/RISCV/double-previous-failure.ll
llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
llvm/test/CodeGen/RISCV/zdinx-memoperand.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 33ec72437a50c..18af1545d5a34 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2576,8 +2576,7 @@ bool RISCVDAGToDAGISel::SelectAddrFrameIndex(SDValue Addr, SDValue &Base,
static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
const MVT VT, const RISCVSubtarget *Subtarget,
SDValue Addr, SDValue &Base, SDValue &Offset,
- bool IsPrefetch = false,
- bool IsRV32Zdinx = false) {
+ bool IsPrefetch = false) {
if (!isa<ConstantSDNode>(Addr))
return false;
@@ -2591,9 +2590,6 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
if (!Subtarget->is64Bit() || isInt<32>(Hi)) {
if (IsPrefetch && (Lo12 & 0b11111) != 0)
return false;
- if (IsRV32Zdinx && !isInt<12>(Lo12 + 4))
- return false;
-
if (Hi) {
int64_t Hi20 = (Hi >> 12) & 0xfffff;
Base = SDValue(
@@ -2617,8 +2613,6 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
Lo12 = Seq.back().getImm();
if (IsPrefetch && (Lo12 & 0b11111) != 0)
return false;
- if (IsRV32Zdinx && !isInt<12>(Lo12 + 4))
- return false;
// Drop the last instruction.
Seq.pop_back();
@@ -2710,7 +2704,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegRegScale(SDValue Addr,
}
bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
- SDValue &Offset, bool IsRV32Zdinx) {
+ SDValue &Offset) {
if (SelectAddrFrameIndex(Addr, Base, Offset))
return true;
@@ -2718,39 +2712,14 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
MVT VT = Addr.getSimpleValueType();
if (Addr.getOpcode() == RISCVISD::ADD_LO) {
- // If this is non RV32Zdinx we can always fold.
- if (!IsRV32Zdinx) {
- Base = Addr.getOperand(0);
- Offset = Addr.getOperand(1);
- return true;
- }
-
- // For RV32Zdinx we need to have more than 4 byte alignment so we can add 4
- // to the offset when we expand in RISCVExpandPseudoInsts.
- if (auto *GA = dyn_cast<GlobalAddressSDNode>(Addr.getOperand(1))) {
- const DataLayout &DL = CurDAG->getDataLayout();
- Align Alignment = commonAlignment(
- GA->getGlobal()->getPointerAlignment(DL), GA->getOffset());
- if (Alignment > 4) {
- Base = Addr.getOperand(0);
- Offset = Addr.getOperand(1);
- return true;
- }
- }
- if (auto *CP = dyn_cast<ConstantPoolSDNode>(Addr.getOperand(1))) {
- Align Alignment = commonAlignment(CP->getAlign(), CP->getOffset());
- if (Alignment > 4) {
- Base = Addr.getOperand(0);
- Offset = Addr.getOperand(1);
- return true;
- }
- }
+ Base = Addr.getOperand(0);
+ Offset = Addr.getOperand(1);
+ return true;
}
- int64_t RV32ZdinxRange = IsRV32Zdinx ? 4 : 0;
if (CurDAG->isBaseWithConstantOffset(Addr)) {
int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
- if (isInt<12>(CVal) && isInt<12>(CVal + RV32ZdinxRange)) {
+ if (isInt<12>(CVal) && isInt<12>(CVal)) {
Base = Addr.getOperand(0);
if (Base.getOpcode() == RISCVISD::ADD_LO) {
SDValue LoOperand = Base.getOperand(1);
@@ -2763,8 +2732,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
const DataLayout &DL = CurDAG->getDataLayout();
Align Alignment = commonAlignment(
GA->getGlobal()->getPointerAlignment(DL), GA->getOffset());
- if ((CVal == 0 || Alignment > CVal) &&
- (!IsRV32Zdinx || commonAlignment(Alignment, CVal) > 4)) {
+ if ((CVal == 0 || Alignment > CVal)) {
int64_t CombinedOffset = CVal + GA->getOffset();
Base = Base.getOperand(0);
Offset = CurDAG->getTargetGlobalAddress(
@@ -2785,13 +2753,13 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
// Handle ADD with large immediates.
if (Addr.getOpcode() == ISD::ADD && isa<ConstantSDNode>(Addr.getOperand(1))) {
int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
- assert(!(isInt<12>(CVal) && isInt<12>(CVal + RV32ZdinxRange)) &&
+ assert(!(isInt<12>(CVal) && isInt<12>(CVal)) &&
"simm12 not already handled?");
// Handle immediates in the range [-4096,-2049] or [2048, 4094]. We can use
// an ADDI for part of the offset and fold the rest into the load/store.
// This mirrors the AddiPair PatFrag in RISCVInstrInfo.td.
- if (CVal >= -4096 && CVal <= (4094 - RV32ZdinxRange)) {
+ if (CVal >= -4096 && CVal <= 4094) {
int64_t Adj = CVal < 0 ? -2048 : 2047;
Base = SDValue(
CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Addr.getOperand(0),
@@ -2809,7 +2777,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
// instructions.
if (isWorthFoldingAdd(Addr) &&
selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr.getOperand(1), Base,
- Offset, /*IsPrefetch=*/false, RV32ZdinxRange)) {
+ Offset, /*IsPrefetch=*/false)) {
// Insert an ADD instruction with the materialized Hi52 bits.
Base = SDValue(
CurDAG->getMachineNode(RISCV::ADD, DL, VT, Addr.getOperand(0), Base),
@@ -2819,7 +2787,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
}
if (selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr, Base, Offset,
- /*IsPrefetch=*/false, RV32ZdinxRange))
+ /*IsPrefetch=*/false))
return true;
Base = Addr;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index cd211d41f30fb..11d62e5edad3f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -46,11 +46,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
std::vector<SDValue> &OutOps) override;
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
- bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset,
- bool IsRV32Zdinx = false);
- bool SelectAddrRegImmRV32Zdinx(SDValue Addr, SDValue &Base, SDValue &Offset) {
- return SelectAddrRegImm(Addr, Base, Offset, true);
- }
+ bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2b385138af458..c56877b9fcfe4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -586,6 +586,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (!Subtarget.is64Bit())
setOperationAction(ISD::BITCAST, MVT::i64, Custom);
+ if (Subtarget.hasStdExtZdinx() && !Subtarget.hasStdExtZilsd() &&
+ !Subtarget.is64Bit()) {
+ setOperationAction(ISD::LOAD, MVT::f64, Custom);
+ setOperationAction(ISD::STORE, MVT::f64, Custom);
+ }
+
if (Subtarget.hasStdExtZfa()) {
setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
setOperationAction(FPRndMode, MVT::f64, Legal);
@@ -7708,19 +7714,42 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
}
case ISD::LOAD: {
auto *Load = cast<LoadSDNode>(Op);
- EVT VecTy = Load->getMemoryVT();
+ EVT VT = Load->getValueType(0);
+ if (VT == MVT::f64) {
+ assert(Subtarget.hasStdExtZdinx() && !Subtarget.hasStdExtZilsd() &&
+ !Subtarget.is64Bit() && "Unexpected custom legalisation");
+
+ // Replace a double precision load with two i32 loads and a BuildPairF64.
+ SDLoc DL(Op);
+ SDValue BasePtr = Load->getBasePtr();
+ SDValue Chain = Load->getChain();
+
+ SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, BasePtr,
+ Load->getPointerInfo(), Load->getOriginalAlign(),
+ Load->getMemOperand()->getFlags());
+ BasePtr = DAG.getObjectPtrOffset(DL, BasePtr, TypeSize::getFixed(4));
+ SDValue Hi = DAG.getLoad(
+ MVT::i32, DL, Chain, BasePtr, Load->getPointerInfo().getWithOffset(4),
+ Load->getOriginalAlign(), Load->getMemOperand()->getFlags());
+ Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
+ Hi.getValue(1));
+
+ SDValue Pair = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
+ return DAG.getMergeValues({Pair, Chain}, DL);
+ }
+
// Handle normal vector tuple load.
- if (VecTy.isRISCVVectorTuple()) {
+ if (VT.isRISCVVectorTuple()) {
SDLoc DL(Op);
MVT XLenVT = Subtarget.getXLenVT();
- unsigned NF = VecTy.getRISCVVectorTupleNumFields();
- unsigned Sz = VecTy.getSizeInBits().getKnownMinValue();
+ unsigned NF = VT.getRISCVVectorTupleNumFields();
+ unsigned Sz = VT.getSizeInBits().getKnownMinValue();
unsigned NumElts = Sz / (NF * 8);
int Log2LMUL = Log2_64(NumElts) - 3;
auto Flag = SDNodeFlags();
Flag.setNoUnsignedWrap(true);
- SDValue Ret = DAG.getUNDEF(VecTy);
+ SDValue Ret = DAG.getUNDEF(VT);
SDValue BasePtr = Load->getBasePtr();
SDValue VROffset = DAG.getNode(RISCVISD::READ_VLENB, DL, XLenVT);
VROffset =
@@ -7734,7 +7763,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
MVT::getScalableVectorVT(MVT::i8, NumElts), DL, Load->getChain(),
BasePtr, MachinePointerInfo(Load->getAddressSpace()), Align(8));
OutChains.push_back(LoadVal.getValue(1));
- Ret = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, VecTy, Ret, LoadVal,
+ Ret = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, VT, Ret, LoadVal,
DAG.getVectorIdxConstant(i, DL));
BasePtr = DAG.getNode(ISD::ADD, DL, XLenVT, BasePtr, VROffset, Flag);
}
@@ -7752,6 +7781,27 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
auto *Store = cast<StoreSDNode>(Op);
SDValue StoredVal = Store->getValue();
EVT VT = StoredVal.getValueType();
+ if (VT == MVT::f64) {
+ assert(Subtarget.hasStdExtZdinx() && !Subtarget.hasStdExtZilsd() &&
+ !Subtarget.is64Bit() && "Unexpected custom legalisation");
+
+ // Replace a double precision store with a SplitF64 and i32 stores.
+ SDValue DL(Op);
+ SDValue BasePtr = Store->getBasePtr();
+ SDValue Chain = Store->getChain();
+ SDValue Split = DAG.getNode(RISCVISD::SplitF64, DL,
+ DAG.getVTList(MVT::i32, MVT::i32), StoredVal);
+
+ SDValue Lo = DAG.getStore(
+ Chain, DL, Split.getValue(0), BasePtr, Store->getPointerInfo(),
+ Store->getOriginalAlign(), Store->getMemOperand()->getFlags());
+ BasePtr = DAG.getObjectPtrOffset(DL, BasePtr, TypeSize::getFixed(4));
+ SDValue Hi = DAG.getStore(Chain, DL, Split.getValue(1), BasePtr,
+ Store->getPointerInfo().getWithOffset(4),
+ Store->getOriginalAlign(),
+ Store->getMemOperand()->getFlags());
+ return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
+ }
if (VT == MVT::i64) {
assert(Subtarget.hasStdExtZilsd() && !Subtarget.is64Bit() &&
"Unexpected custom legalisation");
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index c947252c466f2..414e093510607 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -27,8 +27,6 @@ def : GINodeEquiv<G_MERGE_VALUES, RISCVBuildPairF64>;
def RISCVSplitF64 : RVSDNode<"SplitF64", SDT_RISCVSplitF64>;
def : GINodeEquiv<G_UNMERGE_VALUES, RISCVSplitF64>;
-def AddrRegImmINX : ComplexPattern<iPTR, 2, "SelectAddrRegImmRV32Zdinx">;
-
//===----------------------------------------------------------------------===//
// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//
@@ -529,21 +527,14 @@ defm Select_FPR64IN32X : SelectCC_GPR_rrirr<FPR64IN32X, f64>;
def PseudoFROUND_D_IN32X : PseudoFROUND<FPR64IN32X, f64>;
/// Loads
-let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
/// Stores
-let isCall = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
} // Predicates = [HasStdExtZdinx, IsRV32]
-let Predicates = [HasStdExtZdinx, NoHasStdExtZilsd, IsRV32] in {
-def : Pat<(f64 (load (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12))),
- (PseudoRV32ZdinxLD GPR:$rs1, simm12:$imm12)>;
-def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)),
- (PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>;
-}
-
let Predicates = [HasStdExtZdinx, HasStdExtZilsd, IsRV32] in {
def : LdPat<load, LD_RV32, f64>;
def : StPat<store, SD_RV32, GPRPair, f64>;
diff --git a/llvm/test/CodeGen/RISCV/double-calling-conv.ll b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
index 798eac64e9fc2..1a01fceca75a5 100644
--- a/llvm/test/CodeGen/RISCV/double-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
@@ -165,10 +165,10 @@ define double @callee_double_stack(i64 %a, i64 %b, i64 %c, i64 %d, double %e, do
;
; RV32IZFINXZDINX-LABEL: callee_double_stack:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
+; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
+; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: ret
%1 = fadd double %e, %f
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 03ab83ece8ce7..0716650374d0d 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -734,38 +734,42 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI12_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI12_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: fle.d s2, a4, s0
; RV32IZFINXZDINX-NEXT: call __fixdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
-; RV32IZFINXZDINX-NEXT: fle.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: lui a4, 524288
+; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: lui a2, 524288
-; RV32IZFINXZDINX-NEXT: beqz a3, .LBB12_2
+; RV32IZFINXZDINX-NEXT: beqz s2, .LBB12_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %start
; RV32IZFINXZDINX-NEXT: mv a2, a1
; RV32IZFINXZDINX-NEXT: .LBB12_2: # %start
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI12_1)
-; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI12_1)(a1)
-; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI12_1+4)(a1)
-; RV32IZFINXZDINX-NEXT: flt.d a1, a6, s0
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI12_1)(a1)
+; RV32IZFINXZDINX-NEXT: addi a1, a1, %lo(.LCPI12_1)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a1)
+; RV32IZFINXZDINX-NEXT: flt.d a1, a4, s0
; RV32IZFINXZDINX-NEXT: beqz a1, .LBB12_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
-; RV32IZFINXZDINX-NEXT: addi a2, a4, -1
+; RV32IZFINXZDINX-NEXT: addi a2, a3, -1
; RV32IZFINXZDINX-NEXT: .LBB12_4: # %start
-; RV32IZFINXZDINX-NEXT: feq.d a4, s0, s0
+; RV32IZFINXZDINX-NEXT: feq.d a3, s0, s0
+; RV32IZFINXZDINX-NEXT: neg a4, a1
+; RV32IZFINXZDINX-NEXT: neg a1, s2
; RV32IZFINXZDINX-NEXT: neg a3, a3
-; RV32IZFINXZDINX-NEXT: neg a5, a1
-; RV32IZFINXZDINX-NEXT: neg a4, a4
+; RV32IZFINXZDINX-NEXT: and a0, a1, a0
+; RV32IZFINXZDINX-NEXT: and a1, a3, a2
+; RV32IZFINXZDINX-NEXT: or a0, a4, a0
; RV32IZFINXZDINX-NEXT: and a0, a3, a0
-; RV32IZFINXZDINX-NEXT: and a1, a4, a2
-; RV32IZFINXZDINX-NEXT: or a0, a5, a0
-; RV32IZFINXZDINX-NEXT: and a0, a4, a0
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
@@ -986,12 +990,13 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI14_0)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI14_0+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a4)
+; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI14_0)(a4)
+; RV32IZFINXZDINX-NEXT: addi a3, a4, %lo(.LCPI14_0)
+; RV32IZFINXZDINX-NEXT: lw a7, 4(a3)
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
-; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
+; RV32IZFINXZDINX-NEXT: flt.d a2, a6, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: or a1, a2, a1
@@ -1653,17 +1658,19 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
; RV32IZFINXZDINX: # %bb.0: # %start
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI26_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_0)(a2)
-; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI26_1)
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI26_1+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_1)(a4)
-; RV32IZFINXZDINX-NEXT: fmax.d a2, a0, a2
-; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
-; RV32IZFINXZDINX-NEXT: neg a0, a0
-; RV32IZFINXZDINX-NEXT: fmin.d a2, a2, a4
-; RV32IZFINXZDINX-NEXT: fcvt.w.d a1, a2, rtz
-; RV32IZFINXZDINX-NEXT: and a0, a0, a1
+; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI26_1)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI26_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_1)(a3)
+; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI26_1)
+; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
+; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
+; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
+; RV32IZFINXZDINX-NEXT: neg a1, a6
+; RV32IZFINXZDINX-NEXT: and a0, a1, a0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
@@ -1850,11 +1857,12 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16:
; RV32IZFINXZDINX: # %bb.0: # %start
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI28_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI28_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI28_0)(a2)
-; RV32IZFINXZDINX-NEXT: fcvt.d.w a4, zero
-; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
-; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI28_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI28_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
; RV32IZFINXZDINX-NEXT: ret
;
@@ -2028,17 +2036,19 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
; RV32IZFINXZDINX: # %bb.0: # %start
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI30_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_0)(a2)
-; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI30_1)
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI30_1+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_1)(a4)
-; RV32IZFINXZDINX-NEXT: fmax.d a2, a0, a2
-; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
-; RV32IZFINXZDINX-NEXT: neg a0, a0
-; RV32IZFINXZDINX-NEXT: fmin.d a2, a2, a4
-; RV32IZFINXZDINX-NEXT: fcvt.w.d a1, a2, rtz
-; RV32IZFINXZDINX-NEXT: and a0, a0, a1
+; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI30_1)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI30_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_1)(a3)
+; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI30_1)
+; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
+; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
+; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
+; RV32IZFINXZDINX-NEXT: neg a1, a6
+; RV32IZFINXZDINX-NEXT: and a0, a1, a0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
@@ -2224,11 +2234,12 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
; RV32IZFINXZDINX: # %bb.0: # %start
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI32_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI32_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
-; RV32IZFINXZDINX-NEXT: fcvt.d.w a4, zero
-; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
-; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI32_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI32_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
; RV32IZFINXZDINX-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
index 5350a28005738..d134f8ff16149 100644
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -55,9 +55,10 @@ define double @double_imm_op(double %a) nounwind {
; CHECKRV32ZDINX-LABEL: double_imm_op:
; CHECKRV32ZDINX: # %bb.0:
; CHECKRV32ZDINX-NEXT: lui a2, %hi(.LCPI1_0)
-; CHECKRV32ZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2)
-; CHECKRV32ZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
-; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a2
+; CHECKRV32ZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
+; CHECKRV32ZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
+; CHECKRV32ZDINX-NEXT: lw a5, 4(a2)
+; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a4
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: double_imm_op:
diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll
index b14994dc78ba7..0d02ce127c325 100644
--- a/llvm/test/CodeGen/RISCV/double-mem.ll
+++ b/llvm/test/CodeGen/RISCV/double-mem.ll
@@ -20,9 +20,9 @@ define dso_local double @fld(ptr %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fld:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: lw a2, 0(a0)
; RV32IZFINXZDINX-NEXT: lw a3, 4(a0)
; RV32IZFINXZDINX-NEXT: lw a1, 28(a0)
+; RV32IZFINXZDINX-NEXT: lw a2, 0(a0)
; RV32IZFINXZDINX-NEXT: lw a0, 24(a0)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: ret
@@ -115,13 +115,13 @@ define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: lui a4, %hi(G)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(G)(a4)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(G+4)(a4)
+; RV32IZFINXZDINX-NEXT: lw zero, %lo(G)(a4)
+; RV32IZFINXZDINX-NEXT: lw zero, %lo(G+4)(a4)
; RV32IZFINXZDINX-NEXT: addi a2, a4, %lo(G)
; RV32IZFINXZDINX-NEXT: sw a0, %lo(G)(a4)
; RV32IZFINXZDINX-NEXT: sw a1, %lo(G+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, 72(a2)
-; RV32IZFINXZDINX-NEXT: lw a5, 76(a2)
+; RV32IZFINXZDINX-NEXT: lw zero, 72(a2)
+; RV32IZFINXZDINX-NEXT: lw zero, 76(a2)
; RV32IZFINXZDINX-NEXT: sw a0, 72(a2)
; RV32IZFINXZDINX-NEXT: sw a1, 76(a2)
; RV32IZFINXZDINX-NEXT: ret
@@ -253,8 +253,8 @@ define dso_local double @fld_stack(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: addi a0, sp, 8
; RV32IZFINXZDINX-NEXT: call notdead
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, s0
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
index c5a7ee79364c6..c0993faa9584a 100644
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -51,15 +51,17 @@ define i32 @main() nounwind {
; RV32IZFINXZDINX-NEXT: li a0, 0
; RV32IZFINXZDINX-NEXT: call test
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
-; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a2
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a4
; RV32IZFINXZDINX-NEXT: bnez a2, .LBB1_3
; RV32IZFINXZDINX-NEXT: # %bb.1: # %entry
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_1)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_1+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a2)
-; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_1)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a0
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3
; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end
; RV32IZFINXZDINX-NEXT: call exit
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
index cd87f2d2301d7..e685d21cc0928 100644
--- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
@@ -100,31 +100,33 @@ define i64 @test_floor_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
-; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI1_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a3)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_1+4)(a3)
-; RV32IZFINXZDINX-NEXT: fle.d a6, a4, s0
-; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0
; RV32IZFINXZDINX-NEXT: lui a4, 524288
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: neg a5, a6
-; RV32IZFINXZDINX-NEXT: and a0, a5, a0
-; RV32IZFINXZDINX-NEXT: neg a5, a3
-; RV32IZFINXZDINX-NEXT: or a0, a5, a0
-; RV32IZFINXZDINX-NEXT: lui a5, 524288
-; RV32IZFINXZDINX-NEXT: beqz a6, .LBB1_2
+; RV32IZFINXZDINX-NEXT: lui a2, 524288
+; RV32IZFINXZDINX-NEXT: beqz a3, .LBB1_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
-; RV32IZFINXZDINX-NEXT: mv a5, a1
+; RV32IZFINXZDINX-NEXT: mv a2, a1
; RV32IZFINXZDINX-NEXT: .LBB1_2:
-; RV32IZFINXZDINX-NEXT: and a0, a2, a0
-; RV32IZFINXZDINX-NEXT: beqz a3, .LBB1_4
+; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI1_1)
+; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI1_1)(a1)
+; RV32IZFINXZDINX-NEXT: addi a1, a1, %lo(.LCPI1_1)
+; RV32IZFINXZDINX-NEXT: lw a7, 4(a1)
+; RV32IZFINXZDINX-NEXT: flt.d a1, a6, s0
+; RV32IZFINXZDINX-NEXT: beqz a1, .LBB1_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
-; RV32IZFINXZDINX-NEXT: addi a5, a4, -1
+; RV32IZFINXZDINX-NEXT: addi a2, a4, -1
; RV32IZFINXZDINX-NEXT: .LBB1_4:
-; RV32IZFINXZDINX-NEXT: and a1, a2, a5
+; RV32IZFINXZDINX-NEXT: feq.d a4, s0, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: neg a5, a1
+; RV32IZFINXZDINX-NEXT: neg a4, a4
+; RV32IZFINXZDINX-NEXT: and a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a4, a2
+; RV32IZFINXZDINX-NEXT: or a0, a5, a0
+; RV32IZFINXZDINX-NEXT: and a0, a4, a0
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -217,25 +219,29 @@ define i64 @test_floor_ui64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call floor
+; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI3_0)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI3_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI3_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0
+; RV32IZFINXZDINX-NEXT: neg s2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, s0
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI3_0)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI3_0+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI3_0)(a4)
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
-; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a0, s2, a0
+; RV32IZFINXZDINX-NEXT: or a1, s2, a1
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
@@ -344,31 +350,33 @@ define i64 @test_ceil_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI5_0)
-; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI5_1)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI5_0)(a2)
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI5_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI5_1)(a3)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI5_1+4)(a3)
-; RV32IZFINXZDINX-NEXT: fle.d a6, a4, s0
-; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI5_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0
; RV32IZFINXZDINX-NEXT: lui a4, 524288
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: neg a5, a6
-; RV32IZFINXZDINX-NEXT: and a0, a5, a0
-; RV32IZFINXZDINX-NEXT: neg a5, a3
-; RV32IZFINXZDINX-NEXT: or a0, a5, a0
-; RV32IZFINXZDINX-NEXT: lui a5, 524288
-; RV32IZFINXZDINX-NEXT: beqz a6, .LBB5_2
+; RV32IZFINXZDINX-NEXT: lui a2, 524288
+; RV32IZFINXZDINX-NEXT: beqz a3, .LBB5_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
-; RV32IZFINXZDINX-NEXT: mv a5, a1
+; RV32IZFINXZDINX-NEXT: mv a2, a1
; RV32IZFINXZDINX-NEXT: .LBB5_2:
-; RV32IZFINXZDINX-NEXT: and a0, a2, a0
-; RV32IZFINXZDINX-NEXT: beqz a3, .LBB5_4
+; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI5_1)
+; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI5_1)(a1)
+; RV32IZFINXZDINX-NEXT: addi a1, a1, %lo(.LCPI5_1)
+; RV32IZFINXZDINX-NEXT: lw a7, 4(a1)
+; RV32IZFINXZDINX-NEXT: flt.d a1, a6, s0
+; RV32IZFINXZDINX-NEXT: beqz a1, .LBB5_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
-; RV32IZFINXZDINX-NEXT: addi a5, a4, -1
+; RV32IZFINXZDINX-NEXT: addi a2, a4, -1
; RV32IZFINXZDINX-NEXT: .LBB5_4:
-; RV32IZFINXZDINX-NEXT: and a1, a2, a5
+; RV32IZFINXZDINX-NEXT: feq.d a4, s0, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: neg a5, a1
+; RV32IZFINXZDINX-NEXT: neg a4, a4
+; RV32IZFINXZDINX-NEXT: and a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a4, a2
+; RV32IZFINXZDINX-NEXT: or a0, a5, a0
+; RV32IZFINXZDINX-NEXT: and a0, a4, a0
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -461,25 +469,29 @@ define i64 @test_ceil_ui64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call ceil
+; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI7_0)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI7_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI7_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0
+; RV32IZFINXZDINX-NEXT: neg s2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, s0
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI7_0)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI7_0+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI7_0)(a4)
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
-; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a0, s2, a0
+; RV32IZFINXZDINX-NEXT: or a1, s2, a1
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
@@ -588,31 +600,33 @@ define i64 @test_trunc_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI9_0)
-; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI9_1)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI9_0)(a2)
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI9_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI9_1)(a3)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI9_1+4)(a3)
-; RV32IZFINXZDINX-NEXT: fle.d a6, a4, s0
-; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI9_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0
; RV32IZFINXZDINX-NEXT: lui a4, 524288
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: neg a5, a6
-; RV32IZFINXZDINX-NEXT: and a0, a5, a0
-; RV32IZFINXZDINX-NEXT: neg a5, a3
-; RV32IZFINXZDINX-NEXT: or a0, a5, a0
-; RV32IZFINXZDINX-NEXT: lui a5, 524288
-; RV32IZFINXZDINX-NEXT: beqz a6, .LBB9_2
+; RV32IZFINXZDINX-NEXT: lui a2, 524288
+; RV32IZFINXZDINX-NEXT: beqz a3, .LBB9_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
-; RV32IZFINXZDINX-NEXT: mv a5, a1
+; RV32IZFINXZDINX-NEXT: mv a2, a1
; RV32IZFINXZDINX-NEXT: .LBB9_2:
-; RV32IZFINXZDINX-NEXT: and a0, a2, a0
-; RV32IZFINXZDINX-NEXT: beqz a3, .LBB9_4
+; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI9_1)
+; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI9_1)(a1)
+; RV32IZFINXZDINX-NEXT: addi a1, a1, %lo(.LCPI9_1)
+; RV32IZFINXZDINX-NEXT: lw a7, 4(a1)
+; RV32IZFINXZDINX-NEXT: flt.d a1, a6, s0
+; RV32IZFINXZDINX-NEXT: beqz a1, .LBB9_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
-; RV32IZFINXZDINX-NEXT: addi a5, a4, -1
+; RV32IZFINXZDINX-NEXT: addi a2, a4, -1
; RV32IZFINXZDINX-NEXT: .LBB9_4:
-; RV32IZFINXZDINX-NEXT: and a1, a2, a5
+; RV32IZFINXZDINX-NEXT: feq.d a4, s0, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: neg a5, a1
+; RV32IZFINXZDINX-NEXT: neg a4, a4
+; RV32IZFINXZDINX-NEXT: and a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a4, a2
+; RV32IZFINXZDINX-NEXT: or a0, a5, a0
+; RV32IZFINXZDINX-NEXT: and a0, a4, a0
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -705,25 +719,29 @@ define i64 @test_trunc_ui64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call trunc
+; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI11_0)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI11_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI11_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0
+; RV32IZFINXZDINX-NEXT: neg s2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, s0
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI11_0)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI11_0+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI11_0)(a4)
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
-; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a0, s2, a0
+; RV32IZFINXZDINX-NEXT: or a1, s2, a1
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
@@ -832,31 +850,33 @@ define i64 @test_round_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI13_0)
-; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI13_1)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI13_0)(a2)
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI13_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI13_1)(a3)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI13_1+4)(a3)
-; RV32IZFINXZDINX-NEXT: fle.d a6, a4, s0
-; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI13_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0
; RV32IZFINXZDINX-NEXT: lui a4, 524288
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: neg a5, a6
-; RV32IZFINXZDINX-NEXT: and a0, a5, a0
-; RV32IZFINXZDINX-NEXT: neg a5, a3
-; RV32IZFINXZDINX-NEXT: or a0, a5, a0
-; RV32IZFINXZDINX-NEXT: lui a5, 524288
-; RV32IZFINXZDINX-NEXT: beqz a6, .LBB13_2
+; RV32IZFINXZDINX-NEXT: lui a2, 524288
+; RV32IZFINXZDINX-NEXT: beqz a3, .LBB13_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
-; RV32IZFINXZDINX-NEXT: mv a5, a1
+; RV32IZFINXZDINX-NEXT: mv a2, a1
; RV32IZFINXZDINX-NEXT: .LBB13_2:
-; RV32IZFINXZDINX-NEXT: and a0, a2, a0
-; RV32IZFINXZDINX-NEXT: beqz a3, .LBB13_4
+; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI13_1)
+; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI13_1)(a1)
+; RV32IZFINXZDINX-NEXT: addi a1, a1, %lo(.LCPI13_1)
+; RV32IZFINXZDINX-NEXT: lw a7, 4(a1)
+; RV32IZFINXZDINX-NEXT: flt.d a1, a6, s0
+; RV32IZFINXZDINX-NEXT: beqz a1, .LBB13_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
-; RV32IZFINXZDINX-NEXT: addi a5, a4, -1
+; RV32IZFINXZDINX-NEXT: addi a2, a4, -1
; RV32IZFINXZDINX-NEXT: .LBB13_4:
-; RV32IZFINXZDINX-NEXT: and a1, a2, a5
+; RV32IZFINXZDINX-NEXT: feq.d a4, s0, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: neg a5, a1
+; RV32IZFINXZDINX-NEXT: neg a4, a4
+; RV32IZFINXZDINX-NEXT: and a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a4, a2
+; RV32IZFINXZDINX-NEXT: or a0, a5, a0
+; RV32IZFINXZDINX-NEXT: and a0, a4, a0
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -949,25 +969,29 @@ define i64 @test_round_ui64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call round
+; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI15_0)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI15_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI15_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0
+; RV32IZFINXZDINX-NEXT: neg s2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, s0
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI15_0)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI15_0+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI15_0)(a4)
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
-; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a0, s2, a0
+; RV32IZFINXZDINX-NEXT: or a1, s2, a1
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
@@ -1076,31 +1100,33 @@ define i64 @test_roundeven_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI17_0)
-; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI17_1)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI17_0)(a2)
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI17_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI17_1)(a3)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI17_1+4)(a3)
-; RV32IZFINXZDINX-NEXT: fle.d a6, a4, s0
-; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI17_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0
; RV32IZFINXZDINX-NEXT: lui a4, 524288
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: neg a5, a6
-; RV32IZFINXZDINX-NEXT: and a0, a5, a0
-; RV32IZFINXZDINX-NEXT: neg a5, a3
-; RV32IZFINXZDINX-NEXT: or a0, a5, a0
-; RV32IZFINXZDINX-NEXT: lui a5, 524288
-; RV32IZFINXZDINX-NEXT: beqz a6, .LBB17_2
+; RV32IZFINXZDINX-NEXT: lui a2, 524288
+; RV32IZFINXZDINX-NEXT: beqz a3, .LBB17_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
-; RV32IZFINXZDINX-NEXT: mv a5, a1
+; RV32IZFINXZDINX-NEXT: mv a2, a1
; RV32IZFINXZDINX-NEXT: .LBB17_2:
-; RV32IZFINXZDINX-NEXT: and a0, a2, a0
-; RV32IZFINXZDINX-NEXT: beqz a3, .LBB17_4
+; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI17_1)
+; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI17_1)(a1)
+; RV32IZFINXZDINX-NEXT: addi a1, a1, %lo(.LCPI17_1)
+; RV32IZFINXZDINX-NEXT: lw a7, 4(a1)
+; RV32IZFINXZDINX-NEXT: flt.d a1, a6, s0
+; RV32IZFINXZDINX-NEXT: beqz a1, .LBB17_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
-; RV32IZFINXZDINX-NEXT: addi a5, a4, -1
+; RV32IZFINXZDINX-NEXT: addi a2, a4, -1
; RV32IZFINXZDINX-NEXT: .LBB17_4:
-; RV32IZFINXZDINX-NEXT: and a1, a2, a5
+; RV32IZFINXZDINX-NEXT: feq.d a4, s0, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: neg a5, a1
+; RV32IZFINXZDINX-NEXT: neg a4, a4
+; RV32IZFINXZDINX-NEXT: and a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a4, a2
+; RV32IZFINXZDINX-NEXT: or a0, a5, a0
+; RV32IZFINXZDINX-NEXT: and a0, a4, a0
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -1193,25 +1219,29 @@ define i64 @test_roundeven_ui64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call roundeven
+; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI19_0)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI19_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI19_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0
+; RV32IZFINXZDINX-NEXT: neg s2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, s0
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI19_0)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI19_0+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI19_0)(a4)
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
-; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a0, s2, a0
+; RV32IZFINXZDINX-NEXT: or a1, s2, a1
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
@@ -1320,31 +1350,33 @@ define i64 @test_rint_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI21_0)
-; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI21_1)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI21_0)(a2)
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI21_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI21_1)(a3)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI21_1+4)(a3)
-; RV32IZFINXZDINX-NEXT: fle.d a6, a4, s0
-; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
-; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI21_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
+; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0
; RV32IZFINXZDINX-NEXT: lui a4, 524288
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: neg a5, a6
-; RV32IZFINXZDINX-NEXT: and a0, a5, a0
-; RV32IZFINXZDINX-NEXT: neg a5, a3
-; RV32IZFINXZDINX-NEXT: or a0, a5, a0
-; RV32IZFINXZDINX-NEXT: lui a5, 524288
-; RV32IZFINXZDINX-NEXT: beqz a6, .LBB21_2
+; RV32IZFINXZDINX-NEXT: lui a2, 524288
+; RV32IZFINXZDINX-NEXT: beqz a3, .LBB21_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
-; RV32IZFINXZDINX-NEXT: mv a5, a1
+; RV32IZFINXZDINX-NEXT: mv a2, a1
; RV32IZFINXZDINX-NEXT: .LBB21_2:
-; RV32IZFINXZDINX-NEXT: and a0, a2, a0
-; RV32IZFINXZDINX-NEXT: beqz a3, .LBB21_4
+; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI21_1)
+; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI21_1)(a1)
+; RV32IZFINXZDINX-NEXT: addi a1, a1, %lo(.LCPI21_1)
+; RV32IZFINXZDINX-NEXT: lw a7, 4(a1)
+; RV32IZFINXZDINX-NEXT: flt.d a1, a6, s0
+; RV32IZFINXZDINX-NEXT: beqz a1, .LBB21_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
-; RV32IZFINXZDINX-NEXT: addi a5, a4, -1
+; RV32IZFINXZDINX-NEXT: addi a2, a4, -1
; RV32IZFINXZDINX-NEXT: .LBB21_4:
-; RV32IZFINXZDINX-NEXT: and a1, a2, a5
+; RV32IZFINXZDINX-NEXT: feq.d a4, s0, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: neg a5, a1
+; RV32IZFINXZDINX-NEXT: neg a4, a4
+; RV32IZFINXZDINX-NEXT: and a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a4, a2
+; RV32IZFINXZDINX-NEXT: or a0, a5, a0
+; RV32IZFINXZDINX-NEXT: and a0, a4, a0
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -1437,25 +1469,29 @@ define i64 @test_rint_ui64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call rint
+; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI23_0)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI23_0)(a2)
+; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI23_0)
+; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0
+; RV32IZFINXZDINX-NEXT: neg s2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, s0
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI23_0)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI23_0+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI23_0)(a4)
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
-; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
-; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a0, s2, a0
+; RV32IZFINXZDINX-NEXT: or a1, s2, a1
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
index 9a312d9daca8d..f9db686c9e855 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
+++ b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
@@ -9,20 +9,16 @@
define void @foo(ptr nocapture %p, double %d) nounwind {
; RV32ZDINX-LABEL: foo:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: mv a3, a2
-; RV32ZDINX-NEXT: addi a0, a0, 2047
-; RV32ZDINX-NEXT: mv a2, a1
-; RV32ZDINX-NEXT: sw a2, -3(a0)
-; RV32ZDINX-NEXT: sw a3, 1(a0)
+; RV32ZDINX-NEXT: addi a3, a0, 2044
+; RV32ZDINX-NEXT: sw a1, 2044(a0)
+; RV32ZDINX-NEXT: sw a2, 4(a3)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
-; RV32ZDINXUALIGNED-NEXT: mv a3, a2
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, 2047
-; RV32ZDINXUALIGNED-NEXT: mv a2, a1
-; RV32ZDINXUALIGNED-NEXT: sw a2, -3(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 1(a0)
+; RV32ZDINXUALIGNED-NEXT: addi a3, a0, 2044
+; RV32ZDINXUALIGNED-NEXT: sw a1, 2044(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a3)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo:
@@ -39,21 +35,21 @@ define void @foo2(ptr nocapture %p, double %d) nounwind {
; RV32ZDINX-LABEL: foo2:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: mv a3, a2
-; RV32ZDINX-NEXT: addi a0, a0, 2047
+; RV32ZDINX-NEXT: addi a4, a0, 2044
; RV32ZDINX-NEXT: mv a2, a1
; RV32ZDINX-NEXT: fadd.d a2, a2, a2
-; RV32ZDINX-NEXT: sw a2, -3(a0)
-; RV32ZDINX-NEXT: sw a3, 1(a0)
+; RV32ZDINX-NEXT: sw a3, 4(a4)
+; RV32ZDINX-NEXT: sw a2, 2044(a0)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo2:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: mv a3, a2
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, 2047
+; RV32ZDINXUALIGNED-NEXT: addi a4, a0, 2044
; RV32ZDINXUALIGNED-NEXT: mv a2, a1
; RV32ZDINXUALIGNED-NEXT: fadd.d a2, a2, a2
-; RV32ZDINXUALIGNED-NEXT: sw a2, -3(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 1(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a3, 4(a4)
+; RV32ZDINXUALIGNED-NEXT: sw a2, 2044(a0)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo2:
@@ -74,21 +70,21 @@ define void @foo3(ptr nocapture %p) nounwind {
; RV32ZDINX-LABEL: foo3:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: lui a1, %hi(d)
-; RV32ZDINX-NEXT: lw a2, %lo(d)(a1)
-; RV32ZDINX-NEXT: lw a3, %lo(d+4)(a1)
-; RV32ZDINX-NEXT: addi a0, a0, 2047
-; RV32ZDINX-NEXT: sw a2, -3(a0)
-; RV32ZDINX-NEXT: sw a3, 1(a0)
+; RV32ZDINX-NEXT: lw a2, %lo(d+4)(a1)
+; RV32ZDINX-NEXT: lw a1, %lo(d)(a1)
+; RV32ZDINX-NEXT: addi a3, a0, 2044
+; RV32ZDINX-NEXT: sw a2, 4(a3)
+; RV32ZDINX-NEXT: sw a1, 2044(a0)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo3:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: lui a1, %hi(d)
-; RV32ZDINXUALIGNED-NEXT: lw a2, %lo(d)(a1)
-; RV32ZDINXUALIGNED-NEXT: lw a3, %lo(d+4)(a1)
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, 2047
-; RV32ZDINXUALIGNED-NEXT: sw a2, -3(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 1(a0)
+; RV32ZDINXUALIGNED-NEXT: lw a2, %lo(d+4)(a1)
+; RV32ZDINXUALIGNED-NEXT: lw a1, %lo(d)(a1)
+; RV32ZDINXUALIGNED-NEXT: addi a3, a0, 2044
+; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a3)
+; RV32ZDINXUALIGNED-NEXT: sw a1, 2044(a0)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo3:
@@ -108,26 +104,26 @@ define void @foo4(ptr %p) nounwind {
; RV32ZDINX-LABEL: foo4:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: addi a1, a0, 2047
-; RV32ZDINX-NEXT: lw a2, -3(a1)
-; RV32ZDINX-NEXT: lw a3, 1(a1)
+; RV32ZDINX-NEXT: addi a1, a0, 2044
+; RV32ZDINX-NEXT: lw a2, 2044(a0)
+; RV32ZDINX-NEXT: lw a1, 4(a1)
; RV32ZDINX-NEXT: sw a0, 8(sp)
; RV32ZDINX-NEXT: lui a0, %hi(d)
; RV32ZDINX-NEXT: sw a2, %lo(d)(a0)
-; RV32ZDINX-NEXT: sw a3, %lo(d+4)(a0)
+; RV32ZDINX-NEXT: sw a1, %lo(d+4)(a0)
; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo4:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, -16
-; RV32ZDINXUALIGNED-NEXT: addi a1, a0, 2047
-; RV32ZDINXUALIGNED-NEXT: lw a2, -3(a1)
-; RV32ZDINXUALIGNED-NEXT: lw a3, 1(a1)
+; RV32ZDINXUALIGNED-NEXT: addi a1, a0, 2044
+; RV32ZDINXUALIGNED-NEXT: lw a2, 2044(a0)
+; RV32ZDINXUALIGNED-NEXT: lw a1, 4(a1)
; RV32ZDINXUALIGNED-NEXT: sw a0, 8(sp)
; RV32ZDINXUALIGNED-NEXT: lui a0, %hi(d)
; RV32ZDINXUALIGNED-NEXT: sw a2, %lo(d)(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, %lo(d+4)(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a1, %lo(d+4)(a0)
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, 16
; RV32ZDINXUALIGNED-NEXT: ret
;
@@ -153,20 +149,16 @@ entry:
define void @foo5(ptr nocapture %p, double %d) nounwind {
; RV32ZDINX-LABEL: foo5:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: mv a3, a2
-; RV32ZDINX-NEXT: addi a0, a0, -2048
-; RV32ZDINX-NEXT: mv a2, a1
-; RV32ZDINX-NEXT: sw a2, -1(a0)
-; RV32ZDINX-NEXT: sw a3, 3(a0)
+; RV32ZDINX-NEXT: addi a3, a0, -2048
+; RV32ZDINX-NEXT: sw a2, -2045(a0)
+; RV32ZDINX-NEXT: sw a1, -1(a3)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo5:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
-; RV32ZDINXUALIGNED-NEXT: mv a3, a2
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, -2048
-; RV32ZDINXUALIGNED-NEXT: mv a2, a1
-; RV32ZDINXUALIGNED-NEXT: sw a2, -1(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 3(a0)
+; RV32ZDINXUALIGNED-NEXT: addi a3, a0, -2048
+; RV32ZDINXUALIGNED-NEXT: sw a2, -2045(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a1, -1(a3)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo5:
@@ -186,12 +178,13 @@ define void @foo6(ptr %p, double %d) nounwind {
; RV32ZDINX-NEXT: mv a3, a2
; RV32ZDINX-NEXT: lui a2, %hi(.LCPI5_0)
; RV32ZDINX-NEXT: lw a4, %lo(.LCPI5_0)(a2)
-; RV32ZDINX-NEXT: lw a5, %lo(.LCPI5_0+4)(a2)
+; RV32ZDINX-NEXT: addi a2, a2, %lo(.LCPI5_0)
+; RV32ZDINX-NEXT: lw a5, 4(a2)
; RV32ZDINX-NEXT: mv a2, a1
+; RV32ZDINX-NEXT: addi a1, a0, 2044
; RV32ZDINX-NEXT: fadd.d a2, a2, a4
-; RV32ZDINX-NEXT: addi a0, a0, 2047
-; RV32ZDINX-NEXT: sw a2, -3(a0)
-; RV32ZDINX-NEXT: sw a3, 1(a0)
+; RV32ZDINX-NEXT: sw a3, 4(a1)
+; RV32ZDINX-NEXT: sw a2, 2044(a0)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo6:
@@ -199,12 +192,13 @@ define void @foo6(ptr %p, double %d) nounwind {
; RV32ZDINXUALIGNED-NEXT: mv a3, a2
; RV32ZDINXUALIGNED-NEXT: lui a2, %hi(.LCPI5_0)
; RV32ZDINXUALIGNED-NEXT: lw a4, %lo(.LCPI5_0)(a2)
-; RV32ZDINXUALIGNED-NEXT: lw a5, %lo(.LCPI5_0+4)(a2)
+; RV32ZDINXUALIGNED-NEXT: addi a2, a2, %lo(.LCPI5_0)
+; RV32ZDINXUALIGNED-NEXT: lw a5, 4(a2)
; RV32ZDINXUALIGNED-NEXT: mv a2, a1
+; RV32ZDINXUALIGNED-NEXT: addi a1, a0, 2044
; RV32ZDINXUALIGNED-NEXT: fadd.d a2, a2, a4
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, 2047
-; RV32ZDINXUALIGNED-NEXT: sw a2, -3(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 1(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a3, 4(a1)
+; RV32ZDINXUALIGNED-NEXT: sw a2, 2044(a0)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo6:
@@ -224,30 +218,24 @@ entry:
define void @foo7(ptr nocapture %p) nounwind {
; RV32ZDINX-LABEL: foo7:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: addi sp, sp, -16
; RV32ZDINX-NEXT: lui a1, %hi(d)
-; RV32ZDINX-NEXT: lw a2, %lo(d+4)(a1)
-; RV32ZDINX-NEXT: addi a1, a1, %lo(d)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 8(a1)
-; RV32ZDINX-NEXT: sw a1, 12(sp)
-; RV32ZDINX-NEXT: lw a2, 8(sp)
-; RV32ZDINX-NEXT: lw a3, 12(sp)
-; RV32ZDINX-NEXT: addi a0, a0, 2047
-; RV32ZDINX-NEXT: sw a2, -3(a0)
-; RV32ZDINX-NEXT: sw a3, 1(a0)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: addi a2, a1, %lo(d)
+; RV32ZDINX-NEXT: lw a1, %lo(d+4)(a1)
+; RV32ZDINX-NEXT: lw a2, 8(a2)
+; RV32ZDINX-NEXT: addi a3, a0, 2044
+; RV32ZDINX-NEXT: sw a1, 2044(a0)
+; RV32ZDINX-NEXT: sw a2, 4(a3)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo7:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: lui a1, %hi(d)
-; RV32ZDINXUALIGNED-NEXT: addi a1, a1, %lo(d)
-; RV32ZDINXUALIGNED-NEXT: lw a2, 4(a1)
-; RV32ZDINXUALIGNED-NEXT: lw a3, 8(a1)
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, 2047
-; RV32ZDINXUALIGNED-NEXT: sw a2, -3(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 1(a0)
+; RV32ZDINXUALIGNED-NEXT: addi a2, a1, %lo(d)
+; RV32ZDINXUALIGNED-NEXT: lw a1, %lo(d+4)(a1)
+; RV32ZDINXUALIGNED-NEXT: lw a2, 8(a2)
+; RV32ZDINXUALIGNED-NEXT: addi a3, a0, 2044
+; RV32ZDINXUALIGNED-NEXT: sw a1, 2044(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a3)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo7:
@@ -272,32 +260,28 @@ define void @foo8(ptr %p) nounwind {
; RV32ZDINX-LABEL: foo8:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: addi a1, a0, 2047
-; RV32ZDINX-NEXT: lw a2, -3(a1)
-; RV32ZDINX-NEXT: lw a3, 1(a1)
; RV32ZDINX-NEXT: sw a0, 8(sp)
-; RV32ZDINX-NEXT: sw a2, 0(sp)
-; RV32ZDINX-NEXT: sw a3, 4(sp)
-; RV32ZDINX-NEXT: lw a0, 4(sp)
-; RV32ZDINX-NEXT: lui a1, %hi(d)
-; RV32ZDINX-NEXT: addi a2, a1, %lo(d)
-; RV32ZDINX-NEXT: sw a0, 8(a2)
-; RV32ZDINX-NEXT: lw a0, 0(sp)
-; RV32ZDINX-NEXT: sw a0, %lo(d+4)(a1)
+; RV32ZDINX-NEXT: addi a1, a0, 2044
+; RV32ZDINX-NEXT: lw a0, 2044(a0)
+; RV32ZDINX-NEXT: lw a1, 4(a1)
+; RV32ZDINX-NEXT: lui a2, %hi(d)
+; RV32ZDINX-NEXT: addi a3, a2, %lo(d)
+; RV32ZDINX-NEXT: sw a0, %lo(d+4)(a2)
+; RV32ZDINX-NEXT: sw a1, 8(a3)
; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo8:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, -16
-; RV32ZDINXUALIGNED-NEXT: addi a1, a0, 2047
-; RV32ZDINXUALIGNED-NEXT: lw a2, -3(a1)
-; RV32ZDINXUALIGNED-NEXT: lw a3, 1(a1)
; RV32ZDINXUALIGNED-NEXT: sw a0, 8(sp)
-; RV32ZDINXUALIGNED-NEXT: lui a0, %hi(d)
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, %lo(d)
-; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 8(a0)
+; RV32ZDINXUALIGNED-NEXT: addi a1, a0, 2044
+; RV32ZDINXUALIGNED-NEXT: lw a0, 2044(a0)
+; RV32ZDINXUALIGNED-NEXT: lw a1, 4(a1)
+; RV32ZDINXUALIGNED-NEXT: lui a2, %hi(d)
+; RV32ZDINXUALIGNED-NEXT: addi a3, a2, %lo(d)
+; RV32ZDINXUALIGNED-NEXT: sw a0, %lo(d+4)(a2)
+; RV32ZDINXUALIGNED-NEXT: sw a1, 8(a3)
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, 16
; RV32ZDINXUALIGNED-NEXT: ret
;
@@ -329,30 +313,24 @@ entry:
define void @foo9(ptr nocapture %p) nounwind {
; RV32ZDINX-LABEL: foo9:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: addi sp, sp, -16
; RV32ZDINX-NEXT: lui a1, %hi(e)
-; RV32ZDINX-NEXT: lw a2, %lo(e)(a1)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: addi a1, a1, %lo(e)
-; RV32ZDINX-NEXT: lw a1, 4(a1)
-; RV32ZDINX-NEXT: sw a1, 12(sp)
-; RV32ZDINX-NEXT: lw a2, 8(sp)
-; RV32ZDINX-NEXT: lw a3, 12(sp)
-; RV32ZDINX-NEXT: addi a0, a0, 2047
-; RV32ZDINX-NEXT: sw a2, -3(a0)
-; RV32ZDINX-NEXT: sw a3, 1(a0)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: addi a2, a1, %lo(e)
+; RV32ZDINX-NEXT: lw a1, %lo(e)(a1)
+; RV32ZDINX-NEXT: lw a2, 4(a2)
+; RV32ZDINX-NEXT: addi a3, a0, 2044
+; RV32ZDINX-NEXT: sw a1, 2044(a0)
+; RV32ZDINX-NEXT: sw a2, 4(a3)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo9:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: lui a1, %hi(e)
-; RV32ZDINXUALIGNED-NEXT: addi a1, a1, %lo(e)
-; RV32ZDINXUALIGNED-NEXT: lw a2, 0(a1)
-; RV32ZDINXUALIGNED-NEXT: lw a3, 4(a1)
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, 2047
-; RV32ZDINXUALIGNED-NEXT: sw a2, -3(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 1(a0)
+; RV32ZDINXUALIGNED-NEXT: addi a2, a1, %lo(e)
+; RV32ZDINXUALIGNED-NEXT: lw a1, %lo(e)(a1)
+; RV32ZDINXUALIGNED-NEXT: lw a2, 4(a2)
+; RV32ZDINXUALIGNED-NEXT: addi a3, a0, 2044
+; RV32ZDINXUALIGNED-NEXT: sw a1, 2044(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a3)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo9:
@@ -376,32 +354,28 @@ define void @foo10(ptr %p) nounwind {
; RV32ZDINX-LABEL: foo10:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: addi a1, a0, 2047
-; RV32ZDINX-NEXT: lw a2, -3(a1)
-; RV32ZDINX-NEXT: lw a3, 1(a1)
; RV32ZDINX-NEXT: sw a0, 8(sp)
-; RV32ZDINX-NEXT: sw a2, 0(sp)
-; RV32ZDINX-NEXT: sw a3, 4(sp)
-; RV32ZDINX-NEXT: lw a0, 4(sp)
-; RV32ZDINX-NEXT: lui a1, %hi(e)
-; RV32ZDINX-NEXT: addi a2, a1, %lo(e)
-; RV32ZDINX-NEXT: sw a0, 4(a2)
-; RV32ZDINX-NEXT: lw a0, 0(sp)
-; RV32ZDINX-NEXT: sw a0, %lo(e)(a1)
+; RV32ZDINX-NEXT: lw a1, 2044(a0)
+; RV32ZDINX-NEXT: addi a0, a0, 2044
+; RV32ZDINX-NEXT: lw a0, 4(a0)
+; RV32ZDINX-NEXT: lui a2, %hi(e)
+; RV32ZDINX-NEXT: sw a1, %lo(e)(a2)
+; RV32ZDINX-NEXT: addi a1, a2, %lo(e)
+; RV32ZDINX-NEXT: sw a0, 4(a1)
; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo10:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, -16
-; RV32ZDINXUALIGNED-NEXT: addi a1, a0, 2047
-; RV32ZDINXUALIGNED-NEXT: lw a2, -3(a1)
-; RV32ZDINXUALIGNED-NEXT: lw a3, 1(a1)
; RV32ZDINXUALIGNED-NEXT: sw a0, 8(sp)
-; RV32ZDINXUALIGNED-NEXT: lui a0, %hi(e)
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, %lo(e)
-; RV32ZDINXUALIGNED-NEXT: sw a2, 0(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 4(a0)
+; RV32ZDINXUALIGNED-NEXT: lw a1, 2044(a0)
+; RV32ZDINXUALIGNED-NEXT: addi a0, a0, 2044
+; RV32ZDINXUALIGNED-NEXT: lw a0, 4(a0)
+; RV32ZDINXUALIGNED-NEXT: lui a2, %hi(e)
+; RV32ZDINXUALIGNED-NEXT: sw a1, %lo(e)(a2)
+; RV32ZDINXUALIGNED-NEXT: addi a1, a2, %lo(e)
+; RV32ZDINXUALIGNED-NEXT: sw a0, 4(a1)
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, 16
; RV32ZDINXUALIGNED-NEXT: ret
;
@@ -430,22 +404,18 @@ entry:
define void @foo11(ptr nocapture %p, double %d) nounwind {
; RV32ZDINX-LABEL: foo11:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: mv a3, a2
-; RV32ZDINX-NEXT: lui a2, 1
-; RV32ZDINX-NEXT: add a0, a0, a2
-; RV32ZDINX-NEXT: mv a2, a1
-; RV32ZDINX-NEXT: sw a2, -4(a0)
-; RV32ZDINX-NEXT: sw a3, 0(a0)
+; RV32ZDINX-NEXT: addi a0, a0, 2047
+; RV32ZDINX-NEXT: addi a3, a0, 2045
+; RV32ZDINX-NEXT: sw a1, 2045(a0)
+; RV32ZDINX-NEXT: sw a2, 4(a3)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo11:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
-; RV32ZDINXUALIGNED-NEXT: mv a3, a2
-; RV32ZDINXUALIGNED-NEXT: lui a2, 1
-; RV32ZDINXUALIGNED-NEXT: add a0, a0, a2
-; RV32ZDINXUALIGNED-NEXT: mv a2, a1
-; RV32ZDINXUALIGNED-NEXT: sw a2, -4(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 0(a0)
+; RV32ZDINXUALIGNED-NEXT: addi a0, a0, 2047
+; RV32ZDINXUALIGNED-NEXT: addi a3, a0, 2045
+; RV32ZDINXUALIGNED-NEXT: sw a1, 2045(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a3)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo11:
@@ -462,24 +432,20 @@ entry:
define void @foo12(ptr nocapture %p, double %d) nounwind {
; RV32ZDINX-LABEL: foo12:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: mv a3, a2
-; RV32ZDINX-NEXT: lui a2, 2
-; RV32ZDINX-NEXT: addi a2, a2, 2047
-; RV32ZDINX-NEXT: add a0, a0, a2
-; RV32ZDINX-NEXT: mv a2, a1
-; RV32ZDINX-NEXT: sw a2, 0(a0)
-; RV32ZDINX-NEXT: sw a3, 4(a0)
+; RV32ZDINX-NEXT: lui a3, 2
+; RV32ZDINX-NEXT: addi a3, a3, 2047
+; RV32ZDINX-NEXT: add a0, a0, a3
+; RV32ZDINX-NEXT: sw a1, 0(a0)
+; RV32ZDINX-NEXT: sw a2, 4(a0)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo12:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
-; RV32ZDINXUALIGNED-NEXT: mv a3, a2
-; RV32ZDINXUALIGNED-NEXT: lui a2, 2
-; RV32ZDINXUALIGNED-NEXT: addi a2, a2, 2047
-; RV32ZDINXUALIGNED-NEXT: add a0, a0, a2
-; RV32ZDINXUALIGNED-NEXT: mv a2, a1
-; RV32ZDINXUALIGNED-NEXT: sw a2, 0(a0)
-; RV32ZDINXUALIGNED-NEXT: sw a3, 4(a0)
+; RV32ZDINXUALIGNED-NEXT: lui a3, 2
+; RV32ZDINXUALIGNED-NEXT: addi a3, a3, 2047
+; RV32ZDINXUALIGNED-NEXT: add a0, a0, a3
+; RV32ZDINXUALIGNED-NEXT: sw a1, 0(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a0)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo12:
@@ -499,23 +465,16 @@ entry:
define double @foo13(ptr nocapture %p) nounwind {
; RV32ZDINX-LABEL: foo13:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: lui a0, %hi(f)
-; RV32ZDINX-NEXT: lw a1, %lo(f+8)(a0)
-; RV32ZDINX-NEXT: sw a1, 12(sp)
-; RV32ZDINX-NEXT: lw a0, %lo(f+4)(a0)
-; RV32ZDINX-NEXT: sw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: lui a1, %hi(f)
+; RV32ZDINX-NEXT: lw a0, %lo(f+4)(a1)
+; RV32ZDINX-NEXT: lw a1, %lo(f+8)(a1)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo13:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
-; RV32ZDINXUALIGNED-NEXT: lui a0, %hi(f)
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, %lo(f)
-; RV32ZDINXUALIGNED-NEXT: lw a1, 8(a0)
-; RV32ZDINXUALIGNED-NEXT: lw a0, 4(a0)
+; RV32ZDINXUALIGNED-NEXT: lui a1, %hi(f)
+; RV32ZDINXUALIGNED-NEXT: lw a0, %lo(f+4)(a1)
+; RV32ZDINXUALIGNED-NEXT: lw a1, %lo(f+8)(a1)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo13:
@@ -535,16 +494,16 @@ entry:
define double @foo14(ptr nocapture %p) nounwind {
; RV32ZDINX-LABEL: foo14:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: lui a0, %hi(f)
-; RV32ZDINX-NEXT: lw a1, %lo(f+12)(a0)
-; RV32ZDINX-NEXT: lw a0, %lo(f+8)(a0)
+; RV32ZDINX-NEXT: lui a1, %hi(f)
+; RV32ZDINX-NEXT: lw a0, %lo(f+8)(a1)
+; RV32ZDINX-NEXT: lw a1, %lo(f+12)(a1)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo14:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
-; RV32ZDINXUALIGNED-NEXT: lui a0, %hi(f)
-; RV32ZDINXUALIGNED-NEXT: lw a1, %lo(f+12)(a0)
-; RV32ZDINXUALIGNED-NEXT: lw a0, %lo(f+8)(a0)
+; RV32ZDINXUALIGNED-NEXT: lui a1, %hi(f)
+; RV32ZDINXUALIGNED-NEXT: lw a0, %lo(f+8)(a1)
+; RV32ZDINXUALIGNED-NEXT: lw a1, %lo(f+12)(a1)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo14:
diff --git a/llvm/test/CodeGen/RISCV/zdinx-memoperand.ll b/llvm/test/CodeGen/RISCV/zdinx-memoperand.ll
index d618253912470..8cb7b79f3ff6a 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-memoperand.ll
+++ b/llvm/test/CodeGen/RISCV/zdinx-memoperand.ll
@@ -15,9 +15,8 @@ define i32 @foo(double %x, ptr %y, i64 %0, i64 %1, i1 %cmp6.not, ptr %arrayidx13
; CHECK-NEXT: .LBB0_2: # %if.then7
; CHECK-NEXT: lw a0, 0(sp)
; CHECK-NEXT: .LBB0_3: # %common.ret
-; CHECK-NEXT: fcvt.d.w a2, zero
-; CHECK-NEXT: sw a2, 0(a0)
-; CHECK-NEXT: sw a3, 4(a0)
+; CHECK-NEXT: sw zero, 0(a0)
+; CHECK-NEXT: sw zero, 4(a0)
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
entry:
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