[llvm] [AArch64] Allow lowering of more types to GET_ACTIVE_LANE_MASK (PR #140062)

[David Sherwood via llvm-commits]

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@@ -6595,6 +6617,11 @@ SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_REVERSE(SDNode *N) {
                               Mask);
 }
 
+SDValue DAGTypeLegalizer::WidenVecRes_GET_ACTIVE_LANE_MASK(SDNode *N) {
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  return DAG.getNode(ISD::GET_ACTIVE_LANE_MASK, SDLoc(N), NVT, N->ops());
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david-arm wrote:

Do you know which tests trigger the widening code here - I assume it's `@lane_mask_nxv7i1_i64`? I wonder what happens if the IR then tries to extract element 7 from the vector? Do you know if this is interpreted as vscale number of contiguous <7 x i1> vectors, i.e. suppose vscale = 2, then the first 14 (out of 16 in the widened vector) are the lanes, or whether it's the first 7 elements out of each 8 element chunk, i.e. with padding at the end of each <7 x i1> chunk?

I assume it's the former, in which case this code looks right!

https://github.com/llvm/llvm-project/pull/140062