[llvm] [LLVM][AArch64] Correctly lower funnel shifts by zero. (PR #140058)

[Paul Walker via llvm-commits]

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@@ -7266,12 +7266,18 @@ static SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) {
     MVT VT = Op.getSimpleValueType();
 
     if (Op.getOpcode() == ISD::FSHL) {
+      if (ShiftNo->isZero())
+        return Op.getOperand(0);
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paulwalker-arm wrote:

I wasn't sure whether to repeat the combine or just bypass the rewrite to `ISD::FSHR` and let the final DAG combiner run do its thing.  However, this way mean we can be sure the result can be isel'd, is about the same code and allows for a better test.

https://github.com/llvm/llvm-project/pull/140058