[llvm] [LLVM][TableGen] Simplify `DagInit::get` (PR #140056)

[Rahul Joshi via llvm-commits]

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@@ -213,8 +213,9 @@ void VarLenInst::buildRec(const DagInit *DI) {
     if (NeedSwap) {
       // Normalization: Hi bit should always be the second argument.
       const Init *const NewArgs[] = {OperandName, LoBit, HiBit};
-      Segments.push_back({NumBits,
-                          DagInit::get(DI->getOperator(), nullptr, NewArgs, {}),
+      // TODO: This creates an invalid DagInit with 3 Args but 0 ArgNames.
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jurahul wrote:

@mshockwave This bug is not triggered today in any TableGen unit tests or actual TD files. While the fix is simple, if this is not useful (We can always require HiBitVal >= LoBitVal) I am thinking we delete this code. Please let me know what you think.

https://github.com/llvm/llvm-project/pull/140056