[llvm] [LoongArch] Introduce `32s` target feature for LA32S ISA extensions (PR #139695)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 15 01:50:41 PDT 2025
================
@@ -102,15 +103,26 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
- // Expand bitreverse.i16 with native-width bitrev and shift for now, before
- // we get to know which of sll and revb.2h is faster.
- setOperationAction(ISD::BITREVERSE, MVT::i8, Custom);
- setOperationAction(ISD::BITREVERSE, GRLenVT, Legal);
-
- // LA32 does not have REVB.2W and REVB.D due to the 64-bit operands, and
- // the narrower REVB.W does not exist. But LA32 does have REVB.2H, so i16
- // and i32 could still be byte-swapped relatively cheaply.
- setOperationAction(ISD::BSWAP, MVT::i16, Custom);
+ // BITREV/REVB requires the 32S feature.
+ if (STI.has32S()) {
+ // Expand bitreverse.i16 with native-width bitrev and shift for now, before
+ // we get to know which of sll and revb.2h is faster.
+ setOperationAction(ISD::BITREVERSE, MVT::i8, Custom);
+ setOperationAction(ISD::BITREVERSE, GRLenVT, Legal);
+
+ // LA32 does not have REVB.2W and REVB.D due to the 64-bit operands, and
+ // the narrower REVB.W does not exist. But LA32 does have REVB.2H, so i16
+ // and i32 could still be byte-swapped relatively cheaply.
+ setOperationAction(ISD::BSWAP, MVT::i16, Custom);
+ } else {
+ setOperationAction(ISD::BSWAP, GRLenVT, Expand);
+ setOperationAction(ISD::CTTZ, GRLenVT, Expand);
+ setOperationAction(ISD::CTLZ, GRLenVT, Expand);
+ setOperationAction(ISD::ROTR, GRLenVT, Expand);
+ setOperationAction(ISD::SELECT, GRLenVT, Custom);
----------------
heiher wrote:
Yeah. I'm certain that wouldn't work. Without a `cmov`-like instruction, we need some custom code to handle the lowering properly.
https://github.com/llvm/llvm-project/pull/139695
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