[llvm] eb5e66b - [RISCV] Change type of Zicbop prefetch operand to GPRMem (#139888)

[via llvm-commits]

Author: Alexander Romanov
Date: 2025-05-15T11:18:22+03:00
New Revision: eb5e66b82d09a5d084700fa5d8713c40d27ed1bd

URL: https://github.com/llvm/llvm-project/commit/eb5e66b82d09a5d084700fa5d8713c40d27ed1bd
DIFF: https://github.com/llvm/llvm-project/commit/eb5e66b82d09a5d084700fa5d8713c40d27ed1bd.diff

LOG: [RISCV] Change type of Zicbop prefetch operand to GPRMem (#139888)

Prior to this commit PREFETCH_* instructions considered their operand
register to be a simple GPR which is not entirely correct as it is a
base address for possible prefetching operation (According to cmobase
v1.0.1)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
index 56c870414596b..e44bdcb4e2f0f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
@@ -37,7 +37,7 @@ class CBO_r<bits<12> optype, string opcodestr>
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
 class Prefetch_ri<bits<5> optype, string opcodestr>
-    : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPR:$rs1, simm12_lsb00000:$imm12),
+    : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPRMem:$rs1, simm12_lsb00000:$imm12),
               opcodestr, "${imm12}(${rs1})"> {
   let Inst{11-7} = 0b00000;
   let rs2 = optype;