[llvm] [RISCV][Scheduler] Add scheduling definitions for 128-bit Zfa instructions (PR #140003)

[Pengcheng Wang via llvm-commits]

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@@ -283,12 +283,14 @@ let Latency = 2 in {
   def : WriteRes<WriteFRoundF16, [GenericOOOFPU]>;
   def : WriteRes<WriteFRoundF32, [GenericOOOFPU]>;
   def : WriteRes<WriteFRoundF64, [GenericOOOFPU]>;
+  def : WriteRes<WriteFRoundF128, [GenericOOOFPU]>;
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wangpc-pp wrote:

It feels weird if the hardware doesn't support Q but we need to define the schedule resources for it.

https://github.com/llvm/llvm-project/pull/140003