[llvm] [LoongArch] Introduce `32s` target feature for LA32S ISA extensions (PR #139695)

[WÁNG Xuěruì via llvm-commits]

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@@ -880,12 +853,53 @@ def SYSCALL : MISC_I15<0x002b0000>;
 def BREAK   : MISC_I15<0x002a0000>;
 def RDTIMEL_W : RDTIME_2R<0x00006000>;
 def RDTIMEH_W : RDTIME_2R<0x00006400>;
-def CPUCFG : ALU_2R<0x00006c00>;
 
 // Cache Maintenance Instructions
 def CACOP : FmtCACOP<(outs), (ins uimm5:$op, GPR:$rj, simm12:$imm12),
                      "$op, $rj, $imm12">;
 
+let Predicates = [Has32S] in {
+// Arithmetic Operation Instructions
+def ALSL_W : ALU_3RI2<0x00040000, uimm2_plus1>;
+def ANDN : ALU_3R<0x00168000>;
+def ORN  : ALU_3R<0x00160000>;
+def PCADDI    : ALU_1RI20<0x18000000, simm20_pcaddi>;
+def PCALAU12I : ALU_1RI20<0x1a000000, simm20_pcalau12i>;
+
+// Bit-shift Instructions
+def ROTR_W : ALU_3R<0x001b0000>;
+def ROTRI_W : ALU_2RI5<0x004c8000, uimm5>;
+
+// Bit-manipulation Instructions
+def EXT_W_B : ALU_2R<0x00005c00>;
+def EXT_W_H : ALU_2R<0x00005800>;
+def CLO_W   : ALU_2R<0x00001000>;
+def CLZ_W   : ALU_2R<0x00001400>;
+def CTO_W   : ALU_2R<0x00001800>;
+def CTZ_W   : ALU_2R<0x00001c00>;
+def BYTEPICK_W : ALU_3RI2<0x00080000, uimm2>;
+def REVB_2H   : ALU_2R<0x00003000>;
+def BITREV_4B : ALU_2R<0x00004800>;
+def BITREV_W  : ALU_2R<0x00005000>;
+let Constraints = "$rd = $dst" in {
+def BSTRINS_W  : FmtBSTR_W<0x00600000, (outs GPR:$dst),
+                           (ins GPR:$rd, GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
+                           "$rd, $rj, $msbw, $lsbw">;
+}
+def BSTRPICK_W : FmtBSTR_W<0x00608000, (outs GPR:$rd),
+                           (ins GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
+                           "$rd, $rj, $msbw, $lsbw">;
+def MASKEQZ : ALU_3R<0x00130000>;
+def MASKNEZ : ALU_3R<0x00138000>;
+
+// Branch Instructions
+def BEQZ : BrCCZ_1RI21<0x40000000>;
+def BNEZ : BrCCZ_1RI21<0x44000000>;
+
+// Other Miscellaneous Instructions
+def CPUCFG : ALU_2R<0x00006c00>;
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xen0n wrote:

> Yup, I think the same for IOCSR (probably all privileged instructions).

We can do it in a separate PR.

https://github.com/llvm/llvm-project/pull/139695