[llvm] [AArch64] Stop reserved registers from being saved in prolog/epilog (PR #138448)

[Nuko Y. via llvm-commits]

yasuna-oribe wrote:

I've opened #140005 that disables machine-verifier for the test (apparently there are quite some tests that do this, so I assume it's OK to do) and hopefully fixes the performance regression by computing the BitVectors upfront. I've tested it locally with expensive-checks so it shouldn't cause issues this time.

https://github.com/llvm/llvm-project/pull/138448