[llvm] [WIP][CodeGen] Modifying MBB's liveins representation as into regUnits (PR #129847)

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git-clang-format --diff HEAD~1 HEAD --extensions h,cpp -- llvm/include/llvm/CodeGen/LivePhysRegs.h llvm/include/llvm/CodeGen/MachineBasicBlock.h llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/lib/CodeGen/BranchFolding.cpp llvm/lib/CodeGen/BranchRelaxation.cpp llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp llvm/lib/CodeGen/LiveIntervals.cpp llvm/lib/CodeGen/LivePhysRegs.cpp llvm/lib/CodeGen/LiveRegUnits.cpp llvm/lib/CodeGen/LiveVariables.cpp llvm/lib/CodeGen/MIRPrinter.cpp llvm/lib/CodeGen/MachineBasicBlock.cpp llvm/lib/CodeGen/MachineCopyPropagation.cpp llvm/lib/CodeGen/MachineLICM.cpp llvm/lib/CodeGen/MachineSink.cpp llvm/lib/CodeGen/MachineVerifier.cpp llvm/lib/CodeGen/PrologEpilogInserter.cpp llvm/lib/CodeGen/RDFGraph.cpp llvm/lib/CodeGen/RDFLiveness.cpp llvm/lib/CodeGen/ReachingDefAnalysis.cpp llvm/lib/CodeGen/RegAllocFast.cpp llvm/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/lib/CodeGen/ShrinkWrap.cpp llvm/lib/CodeGen/VirtRegMap.cpp llvm/lib/Target/AArch64/AArch64CollectLOH.cpp llvm/lib/Target/AArch64/AArch64FrameLowering.cpp llvm/lib/Target/AMDGPU/SIFrameLowering.cpp llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp llvm/lib/Target/ARM/ARMConstantIslandPass.cpp llvm/lib/Target/ARM/ARMFrameLowering.cpp llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp llvm/lib/Target/ARM/ThumbRegisterInfo.cpp llvm/lib/Target/AVR/AVRFrameLowering.cpp llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp llvm/lib/Target/M68k/M68kFrameLowering.cpp llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp llvm/lib/Target/X86/X86FloatingPoint.cpp llvm/lib/Target/X86/X86FrameLowering.cpp llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp
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diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 546733d3e..57b9d3960 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -636,7 +636,7 @@ MachineBasicBlock::removeLiveIn(MachineBasicBlock::livein_iterator I) {
 }
 
 bool MachineBasicBlock::isLiveIn(MCRegister Reg, LaneBitmask LaneMask) const {
-  if(!Reg.isPhysical())
+  if (!Reg.isPhysical())
     return false;
 
   const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 206b7cf5d..5f6c45247 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -160,7 +160,7 @@ struct MachineVerifier {
     if (Reg.isPhysical()) {
       for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
         for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
-            ++RootReg)
+             ++RootReg)
           RV.push_back(*RootReg);
     }
   }

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https://github.com/llvm/llvm-project/pull/129847