[llvm] [LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties (PR #140002)

Rahul Joshi via llvm-commits llvm-commits at lists.llvm.org
Wed May 14 22:50:55 PDT 2025


https://github.com/jurahul updated https://github.com/llvm/llvm-project/pull/140002

>From 51fa327eb3646e1f9567c734645e2886fb83ac30 Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Wed, 14 May 2025 18:22:20 -0700
Subject: [PATCH] [LLVM][CodeGen] Add convenience accessors for
 MachineFunctionProperties

Add per-property has<Prop>/set<Prop>/reset<Prop> functions to
MachineFunctionProperties.
---
 llvm/include/llvm/CodeGen/BranchFoldingPass.h |  3 +-
 .../include/llvm/CodeGen/ExecutionDomainFix.h |  3 +-
 .../CodeGen/GlobalISel/InstructionSelect.h    |  9 ++--
 .../llvm/CodeGen/GlobalISel/Legalizer.h       | 10 ++---
 .../llvm/CodeGen/GlobalISel/LoadStoreOpt.h    |  3 +-
 .../llvm/CodeGen/GlobalISel/Localizer.h       |  3 +-
 .../llvm/CodeGen/GlobalISel/RegBankSelect.h   | 10 ++---
 llvm/include/llvm/CodeGen/IndirectThunks.h    |  4 +-
 .../include/llvm/CodeGen/LiveDebugVariables.h |  6 +--
 llvm/include/llvm/CodeGen/MachineCSE.h        |  3 +-
 .../llvm/CodeGen/MachineCopyPropagation.h     |  3 +-
 llvm/include/llvm/CodeGen/MachineFunction.h   | 19 +++++++++
 .../llvm/CodeGen/MachineLateInstrsCleanup.h   |  3 +-
 .../llvm/CodeGen/MachineRegisterInfo.h        | 17 ++------
 llvm/include/llvm/CodeGen/PatchableFunction.h |  3 +-
 .../llvm/CodeGen/PostRASchedulerList.h        |  3 +-
 .../llvm/CodeGen/ReachingDefAnalysis.h        |  4 +-
 llvm/include/llvm/CodeGen/RegAllocFast.h      |  9 ++--
 .../include/llvm/CodeGen/RegAllocGreedyPass.h |  6 +--
 .../llvm/CodeGen/RegisterCoalescerPass.h      |  3 +-
 .../llvm/CodeGen/RemoveLoadsIntoFakeUses.h    |  3 +-
 llvm/include/llvm/CodeGen/ShrinkWrap.h        |  3 +-
 llvm/include/llvm/CodeGen/TailDuplication.h   |  3 +-
 .../llvm/CodeGen/TwoAddressInstructionPass.h  |  3 +-
 llvm/lib/CodeGen/BranchFolding.cpp            |  3 +-
 llvm/lib/CodeGen/BreakFalseDeps.cpp           |  3 +-
 llvm/lib/CodeGen/FuncletLayout.cpp            |  3 +-
 llvm/lib/CodeGen/GlobalISel/Combiner.cpp      |  3 +-
 llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp  |  2 +-
 .../CodeGen/GlobalISel/InstructionSelect.cpp  |  5 +--
 llvm/lib/CodeGen/GlobalISel/Legalizer.cpp     |  3 +-
 llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp  |  6 +--
 llvm/lib/CodeGen/GlobalISel/Localizer.cpp     |  3 +-
 llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp |  3 +-
 llvm/lib/CodeGen/GlobalISel/Utils.cpp         |  2 +-
 llvm/lib/CodeGen/IfConversion.cpp             |  3 +-
 llvm/lib/CodeGen/ImplicitNullChecks.cpp       |  3 +-
 llvm/lib/CodeGen/MIRParser/MIRParser.cpp      | 18 ++++----
 llvm/lib/CodeGen/MIRPrinter.cpp               | 29 +++++--------
 llvm/lib/CodeGen/MachineBasicBlock.cpp        | 10 ++---
 llvm/lib/CodeGen/MachineCSE.cpp               |  3 +-
 llvm/lib/CodeGen/MachineCopyPropagation.cpp   |  3 +-
 llvm/lib/CodeGen/MachineFunction.cpp          |  4 +-
 llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp |  3 +-
 llvm/lib/CodeGen/MachineOutliner.cpp          | 11 +++--
 llvm/lib/CodeGen/MachineSink.cpp              |  3 +-
 llvm/lib/CodeGen/MachineVerifier.cpp          | 42 +++++++------------
 llvm/lib/CodeGen/PHIElimination.cpp           |  5 +--
 llvm/lib/CodeGen/PatchableFunction.cpp        |  3 +-
 llvm/lib/CodeGen/PeepholeOptimizer.cpp        |  3 +-
 llvm/lib/CodeGen/PostRASchedulerList.cpp      |  3 +-
 llvm/lib/CodeGen/ProcessImplicitDefs.cpp      |  3 +-
 llvm/lib/CodeGen/PrologEpilogInserter.cpp     |  3 +-
 llvm/lib/CodeGen/RegAllocBase.cpp             |  5 +--
 llvm/lib/CodeGen/RegAllocBasic.cpp            |  6 +--
 llvm/lib/CodeGen/RegAllocFast.cpp             | 14 +++----
 llvm/lib/CodeGen/RegAllocGreedy.cpp           |  6 +--
 llvm/lib/CodeGen/RegAllocPBQP.cpp             |  6 +--
 llvm/lib/CodeGen/RegisterCoalescer.cpp        |  3 +-
 llvm/lib/CodeGen/RegisterScavenging.cpp       |  4 +-
 llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp  |  3 +-
 llvm/lib/CodeGen/ResetMachineFunctionPass.cpp |  3 +-
 .../CodeGen/SelectionDAG/SelectionDAGISel.cpp |  6 +--
 llvm/lib/CodeGen/ShrinkWrap.cpp               |  3 +-
 llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp |  3 +-
 llvm/lib/CodeGen/TailDuplication.cpp          |  3 +-
 llvm/lib/CodeGen/TargetInstrInfo.cpp          |  3 +-
 .../lib/CodeGen/TwoAddressInstructionPass.cpp |  3 +-
 llvm/lib/CodeGen/VirtRegMap.cpp               |  3 +-
 69 files changed, 152 insertions(+), 246 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/BranchFoldingPass.h b/llvm/include/llvm/CodeGen/BranchFoldingPass.h
index 6ebef47252d25..ae07be28c5962 100644
--- a/llvm/include/llvm/CodeGen/BranchFoldingPass.h
+++ b/llvm/include/llvm/CodeGen/BranchFoldingPass.h
@@ -21,8 +21,7 @@ class BranchFolderPass : public PassInfoMixin<BranchFolderPass> {
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/ExecutionDomainFix.h b/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
index 7cec96bf2851a..6846a3dd84f7c 100644
--- a/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
+++ b/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
@@ -148,8 +148,7 @@ class ExecutionDomainFix : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
index 75f683764d165..894a289b3e6a3 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
@@ -41,14 +41,13 @@ class InstructionSelect : public MachineFunctionPass {
 
   MachineFunctionProperties getRequiredProperties() const override {
     return MachineFunctionProperties()
-        .set(MachineFunctionProperties::Property::IsSSA)
-        .set(MachineFunctionProperties::Property::Legalized)
-        .set(MachineFunctionProperties::Property::RegBankSelected);
+        .setIsSSA()
+        .setLegalized()
+        .setRegBankSelected();
   }
 
   MachineFunctionProperties getSetProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::Selected);
+    return MachineFunctionProperties().setSelected();
   }
 
   InstructionSelect(CodeGenOptLevel OL = CodeGenOptLevel::Default,
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h b/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h
index 15bef84632b7a..4fcc935a75109 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h
@@ -56,19 +56,15 @@ class Legalizer : public MachineFunctionPass {
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   MachineFunctionProperties getSetProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::Legalized);
+    return MachineFunctionProperties().setLegalized();
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties()
-        .set(MachineFunctionProperties::Property::NoPHIs)
-        .set(MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoPHIs().setNoVRegs();
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h b/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h
index 7990997835d01..b93a666ac664e 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h
@@ -169,8 +169,7 @@ class LoadStoreOpt : public MachineFunctionPass {
   StringRef getPassName() const override { return "LoadStoreOpt"; }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties()
-        .set(MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Localizer.h b/llvm/include/llvm/CodeGen/GlobalISel/Localizer.h
index 4fbff4d10f8ab..4c25c9c2a8345 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Localizer.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Localizer.h
@@ -85,8 +85,7 @@ class Localizer : public MachineFunctionPass {
   StringRef getPassName() const override { return "Localizer"; }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties()
-        .set(MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
index 46173ffd76b72..076c70d21bbdf 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
@@ -624,19 +624,15 @@ class RegBankSelect : public MachineFunctionPass {
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties()
-        .set(MachineFunctionProperties::Property::IsSSA)
-        .set(MachineFunctionProperties::Property::Legalized);
+    return MachineFunctionProperties().setIsSSA().setLegalized();
   }
 
   MachineFunctionProperties getSetProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::RegBankSelected);
+    return MachineFunctionProperties().setRegBankSelected();
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties()
-      .set(MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 
   /// Check that our input is fully legal: we require the function to have the
diff --git a/llvm/include/llvm/CodeGen/IndirectThunks.h b/llvm/include/llvm/CodeGen/IndirectThunks.h
index 6c16b326fedd0..c54df87aa8228 100644
--- a/llvm/include/llvm/CodeGen/IndirectThunks.h
+++ b/llvm/include/llvm/CodeGen/IndirectThunks.h
@@ -157,8 +157,8 @@ void ThunkInserter<Derived, InsertedThunksTy>::createThunkFunction(
   // generate one.  At least GlobalISel asserts if this invariant isn't
   // respected.
 
-  // Set MF properties. We never use vregs...
-  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
+  // Set MF properties. We never use vregs.
+  MF.getProperties().setNoVRegs();
 }
 
 template <typename Derived, typename InsertedThunksTy>
diff --git a/llvm/include/llvm/CodeGen/LiveDebugVariables.h b/llvm/include/llvm/CodeGen/LiveDebugVariables.h
index 2cb95f2c71ccd..9d737a8f66c92 100644
--- a/llvm/include/llvm/CodeGen/LiveDebugVariables.h
+++ b/llvm/include/llvm/CodeGen/LiveDebugVariables.h
@@ -88,8 +88,7 @@ class LiveDebugVariablesWrapperLegacy : public MachineFunctionPass {
   void getAnalysisUsage(AnalysisUsage &) const override;
 
   MachineFunctionProperties getSetProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::TracksDebugUserValues);
+    return MachineFunctionProperties().setTracksDebugUserValues();
   }
 };
 
@@ -102,8 +101,7 @@ class LiveDebugVariablesAnalysis
   using Result = LiveDebugVariables;
 
   MachineFunctionProperties getSetProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::TracksDebugUserValues);
+    return MachineFunctionProperties().setTracksDebugUserValues();
   }
 
   Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
diff --git a/llvm/include/llvm/CodeGen/MachineCSE.h b/llvm/include/llvm/CodeGen/MachineCSE.h
index 16a313508547d..b2b0d414ae673 100644
--- a/llvm/include/llvm/CodeGen/MachineCSE.h
+++ b/llvm/include/llvm/CodeGen/MachineCSE.h
@@ -19,8 +19,7 @@ class MachineCSEPass : public PassInfoMixin<MachineCSEPass> {
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/MachineCopyPropagation.h b/llvm/include/llvm/CodeGen/MachineCopyPropagation.h
index 2fe26464b71b3..8355752e747c0 100644
--- a/llvm/include/llvm/CodeGen/MachineCopyPropagation.h
+++ b/llvm/include/llvm/CodeGen/MachineCopyPropagation.h
@@ -25,8 +25,7 @@ class MachineCopyPropagationPass
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 30d414f0829e5..81428c6450529 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -214,6 +214,25 @@ class MachineFunctionProperties {
     return *this;
   }
 
+  // Per property has/set/reset accessors.
+#define PPACCESSORS(X)                                                         \
+  bool has##X() const { return hasProperty(Property::X); }                     \
+  MachineFunctionProperties &set##X(void) { return set(Property::X); }         \
+  MachineFunctionProperties &reset##X(void) { return reset(Property::X); }
+
+  PPACCESSORS(IsSSA)
+  PPACCESSORS(NoPHIs)
+  PPACCESSORS(TracksLiveness)
+  PPACCESSORS(NoVRegs)
+  PPACCESSORS(FailedISel)
+  PPACCESSORS(Legalized)
+  PPACCESSORS(RegBankSelected)
+  PPACCESSORS(Selected)
+  PPACCESSORS(TiedOpsRewritten)
+  PPACCESSORS(FailsVerification)
+  PPACCESSORS(FailedRegAlloc)
+  PPACCESSORS(TracksDebugUserValues)
+
   /// Reset all the properties.
   MachineFunctionProperties &reset() {
     Properties.reset();
diff --git a/llvm/include/llvm/CodeGen/MachineLateInstrsCleanup.h b/llvm/include/llvm/CodeGen/MachineLateInstrsCleanup.h
index 8a539eb1bb271..8562e1ad38a7e 100644
--- a/llvm/include/llvm/CodeGen/MachineLateInstrsCleanup.h
+++ b/llvm/include/llvm/CodeGen/MachineLateInstrsCleanup.h
@@ -19,8 +19,7 @@ class MachineLateInstrsCleanupPass
                         MachineFunctionAnalysisManager &MachineFunctionAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index f20f4b16a5f17..f6c7e4f4a4c8e 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -198,21 +198,15 @@ class MachineRegisterInfo {
   // The TwoAddressInstructionPass and PHIElimination passes take the machine
   // function out of SSA form when they introduce multiple defs per virtual
   // register.
-  bool isSSA() const {
-    return MF->getProperties().hasProperty(
-        MachineFunctionProperties::Property::IsSSA);
-  }
+  bool isSSA() const { return MF->getProperties().hasIsSSA(); }
 
   // leaveSSA - Indicates that the machine function is no longer in SSA form.
-  void leaveSSA() {
-    MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
-  }
+  void leaveSSA() { MF->getProperties().resetIsSSA(); }
 
   /// tracksLiveness - Returns true when tracking register liveness accurately.
   /// (see MachineFUnctionProperties::Property description for details)
   bool tracksLiveness() const {
-    return MF->getProperties().hasProperty(
-        MachineFunctionProperties::Property::TracksLiveness);
+    return MF->getProperties().hasTracksLiveness();
   }
 
   /// invalidateLiveness - Indicates that register liveness is no longer being
@@ -220,10 +214,7 @@ class MachineRegisterInfo {
   ///
   /// This should be called by late passes that invalidate the liveness
   /// information.
-  void invalidateLiveness() {
-    MF->getProperties().reset(
-        MachineFunctionProperties::Property::TracksLiveness);
-  }
+  void invalidateLiveness() { MF->getProperties().resetTracksLiveness(); }
 
   /// Returns true if liveness for register class @p RC should be tracked at
   /// the subregister level.
diff --git a/llvm/include/llvm/CodeGen/PatchableFunction.h b/llvm/include/llvm/CodeGen/PatchableFunction.h
index d81a92f9eef26..095e159010b6c 100644
--- a/llvm/include/llvm/CodeGen/PatchableFunction.h
+++ b/llvm/include/llvm/CodeGen/PatchableFunction.h
@@ -19,8 +19,7 @@ class PatchableFunctionPass : public PassInfoMixin<PatchableFunctionPass> {
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
   static bool isRequired() { return true; }
 };
diff --git a/llvm/include/llvm/CodeGen/PostRASchedulerList.h b/llvm/include/llvm/CodeGen/PostRASchedulerList.h
index 06043bed5c088..e450dc8101078 100644
--- a/llvm/include/llvm/CodeGen/PostRASchedulerList.h
+++ b/llvm/include/llvm/CodeGen/PostRASchedulerList.h
@@ -22,8 +22,7 @@ class PostRASchedulerPass : public PassInfoMixin<PostRASchedulerPass> {
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
index 978e84b09a736..41ea462201ee5 100644
--- a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
+++ b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
@@ -172,9 +172,7 @@ class ReachingDefAnalysis : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs).set(
-          MachineFunctionProperties::Property::TracksLiveness);
+    return MachineFunctionProperties().setNoVRegs().setTracksLiveness();
   }
 
   /// Re-run the analysis.
diff --git a/llvm/include/llvm/CodeGen/RegAllocFast.h b/llvm/include/llvm/CodeGen/RegAllocFast.h
index 83b9125dc07e9..d3a13e22fc8b1 100644
--- a/llvm/include/llvm/CodeGen/RegAllocFast.h
+++ b/llvm/include/llvm/CodeGen/RegAllocFast.h
@@ -28,22 +28,19 @@ class RegAllocFastPass : public PassInfoMixin<RegAllocFastPass> {
   RegAllocFastPass(Options Opts = Options()) : Opts(std::move(Opts)) {}
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 
   MachineFunctionProperties getSetProperties() const {
     if (Opts.ClearVRegs) {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     return MachineFunctionProperties();
   }
 
   MachineFunctionProperties getClearedProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &);
diff --git a/llvm/include/llvm/CodeGen/RegAllocGreedyPass.h b/llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
index d2fd66f8da593..6b34ee3ff2543 100644
--- a/llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
+++ b/llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
@@ -28,13 +28,11 @@ class RAGreedyPass : public PassInfoMixin<RAGreedyPass> {
   PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 
   MachineFunctionProperties getClearedProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   void
diff --git a/llvm/include/llvm/CodeGen/RegisterCoalescerPass.h b/llvm/include/llvm/CodeGen/RegisterCoalescerPass.h
index 91f66dbf33b5f..7211d1e79306e 100644
--- a/llvm/include/llvm/CodeGen/RegisterCoalescerPass.h
+++ b/llvm/include/llvm/CodeGen/RegisterCoalescerPass.h
@@ -18,8 +18,7 @@ class RegisterCoalescerPass : public PassInfoMixin<RegisterCoalescerPass> {
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getClearedProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h b/llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h
index bbd5b8b430bf6..70cd2fe0c3cc4 100644
--- a/llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h
+++ b/llvm/include/llvm/CodeGen/RemoveLoadsIntoFakeUses.h
@@ -20,8 +20,7 @@ class RemoveLoadsIntoFakeUsesPass
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/ShrinkWrap.h b/llvm/include/llvm/CodeGen/ShrinkWrap.h
index 9035847a93dea..805924be306e8 100644
--- a/llvm/include/llvm/CodeGen/ShrinkWrap.h
+++ b/llvm/include/llvm/CodeGen/ShrinkWrap.h
@@ -19,8 +19,7 @@ class ShrinkWrapPass : public PassInfoMixin<ShrinkWrapPass> {
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/TailDuplication.h b/llvm/include/llvm/CodeGen/TailDuplication.h
index 687a592ccf2fb..d1cc4b0d065f0 100644
--- a/llvm/include/llvm/CodeGen/TailDuplication.h
+++ b/llvm/include/llvm/CodeGen/TailDuplication.h
@@ -29,8 +29,7 @@ class EarlyTailDuplicatePass
     : public TailDuplicatePassBase<EarlyTailDuplicatePass, true> {
 public:
   MachineFunctionProperties getClearedProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 };
 
diff --git a/llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h b/llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
index d4d47f29cc844..a51c7c99d9bb3 100644
--- a/llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
+++ b/llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
@@ -19,8 +19,7 @@ class TwoAddressInstructionPass
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
   MachineFunctionProperties getSetProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::TiedOpsRewritten);
+    return MachineFunctionProperties().setTiedOpsRewritten();
   }
 };
 
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index 6f5afbd2a996a..d1663e0fbd544 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -106,8 +106,7 @@ class BranchFolderLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 };
 
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 618e41894b29b..05eed969a18af 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -64,8 +64,7 @@ class BreakFalseDeps : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-      MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:
diff --git a/llvm/lib/CodeGen/FuncletLayout.cpp b/llvm/lib/CodeGen/FuncletLayout.cpp
index f1222a88b054a..f2dd3937bb5a0 100644
--- a/llvm/lib/CodeGen/FuncletLayout.cpp
+++ b/llvm/lib/CodeGen/FuncletLayout.cpp
@@ -29,8 +29,7 @@ class FuncletLayout : public MachineFunctionPass {
 
   bool runOnMachineFunction(MachineFunction &F) override;
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 }
diff --git a/llvm/lib/CodeGen/GlobalISel/Combiner.cpp b/llvm/lib/CodeGen/GlobalISel/Combiner.cpp
index 733ac41b8c7a1..2cba6f0504540 100644
--- a/llvm/lib/CodeGen/GlobalISel/Combiner.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Combiner.cpp
@@ -255,8 +255,7 @@ bool Combiner::tryDCE(MachineInstr &MI, MachineRegisterInfo &MRI) {
 bool Combiner::combineMachineInstrs() {
   // If the ISel pipeline failed, do not bother running this pass.
   // FIXME: Should this be here or in individual combiner passes.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   // We can't call this in the constructor because the derived class is
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 8ab2533afc15f..30153737ac5d0 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -115,7 +115,7 @@ static void reportTranslationError(MachineFunction &MF,
                                    const TargetPassConfig &TPC,
                                    OptimizationRemarkEmitter &ORE,
                                    OptimizationRemarkMissed &R) {
-  MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
+  MF.getProperties().setFailedISel();
 
   // Print the function name explicitly if we don't have a debug location (which
   // makes the diagnostic less useful) or if we're going to emit a raw error.
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
index 194cbc5b2ac87..2dd22c8a7e8ba 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -133,8 +133,7 @@ void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
 
 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
   // If the ISel pipeline failed, do not bother running that pass.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   ISel = MF.getSubtarget().getInstructionSelector();
@@ -307,7 +306,7 @@ bool InstructionSelect::selectMachineFunction(MachineFunction &MF) {
 
   if (!DebugCounter::shouldExecute(GlobalISelCounter)) {
     dbgs() << "Falling back for function " << MF.getName() << "\n";
-    MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
+    MF.getProperties().setFailedISel();
     return false;
   }
 
diff --git a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
index 1bb3f4bcc9b1b..aef16b5f33af4 100644
--- a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
@@ -308,8 +308,7 @@ Legalizer::legalizeMachineFunction(MachineFunction &MF, const LegalizerInfo &LI,
 
 bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
   // If the ISel pipeline failed, do not bother running that pass.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   LLVM_DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
   init(MF);
diff --git a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
index b507c42228465..78cd9bc7891e0 100644
--- a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
@@ -67,8 +67,7 @@ void LoadStoreOpt::init(MachineFunction &MF) {
   TLI = MF.getSubtarget().getTargetLowering();
   LI = MF.getSubtarget().getLegalizerInfo();
   Builder.setMF(MF);
-  IsPreLegalizer = !MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::Legalized);
+  IsPreLegalizer = !MF.getProperties().hasLegalized();
   InstsToErase.clear();
 }
 
@@ -973,8 +972,7 @@ void LoadStoreOpt::initializeStoreMergeTargetInfo(unsigned AddrSpace) {
 
 bool LoadStoreOpt::runOnMachineFunction(MachineFunction &MF) {
   // If the ISel pipeline failed, do not bother running that pass.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   LLVM_DEBUG(dbgs() << "Begin memory optimizations for: " << MF.getName()
diff --git a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
index 5164875689056..77ca27bcc43e2 100644
--- a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
@@ -203,8 +203,7 @@ bool Localizer::localizeIntraBlock(LocalizedSetVecT &LocalizedInstrs) {
 
 bool Localizer::runOnMachineFunction(MachineFunction &MF) {
   // If the ISel pipeline failed, do not bother running that pass.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   // Don't run the pass if the target asked so.
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index f1fec547ebd60..bcb4f1c551cfd 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -733,8 +733,7 @@ bool RegBankSelect::checkFunctionIsLegal(MachineFunction &MF) const {
 
 bool RegBankSelect::runOnMachineFunction(MachineFunction &MF) {
   // If the ISel pipeline failed, do not bother running that pass.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 445a716d20478..64af7a57e8d12 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -259,7 +259,7 @@ void llvm::reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
                               MachineOptimizationRemarkEmitter &MORE,
                               MachineOptimizationRemarkMissed &R) {
-  MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
+  MF.getProperties().setFailedISel();
   reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R);
 }
 
diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp
index 400418e9331e6..5265bd74d2dbf 100644
--- a/llvm/lib/CodeGen/IfConversion.cpp
+++ b/llvm/lib/CodeGen/IfConversion.cpp
@@ -217,8 +217,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
   private:
diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
index 0e0ffa51d647b..b585ce491f62a 100644
--- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp
+++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
@@ -226,8 +226,7 @@ class ImplicitNullChecks : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 6e63f1c375046..a57bda54f9180 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -434,7 +434,7 @@ bool MIRParserImpl::computeFunctionProperties(
   MF.setHasInlineAsm(HasInlineAsm);
 
   if (HasTiedOps && AllTiedOpsRewritten)
-    Properties.set(MachineFunctionProperties::Property::TiedOpsRewritten);
+    Properties.setTiedOpsRewritten();
 
   if (ComputedPropertyHelper(YamlMF.IsSSA, isSSA(MF),
                              MachineFunctionProperties::Property::IsSSA)) {
@@ -556,21 +556,19 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
   MF.setHasEHFunclets(YamlMF.HasEHFunclets);
   MF.setIsOutlined(YamlMF.IsOutlined);
 
+  MachineFunctionProperties &Props = MF.getProperties();
   if (YamlMF.Legalized)
-    MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
+    Props.setLegalized();
   if (YamlMF.RegBankSelected)
-    MF.getProperties().set(
-        MachineFunctionProperties::Property::RegBankSelected);
+    Props.setRegBankSelected();
   if (YamlMF.Selected)
-    MF.getProperties().set(MachineFunctionProperties::Property::Selected);
+    Props.setSelected();
   if (YamlMF.FailedISel)
-    MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
+    Props.setFailedISel();
   if (YamlMF.FailsVerification)
-    MF.getProperties().set(
-        MachineFunctionProperties::Property::FailsVerification);
+    Props.setFailsVerification();
   if (YamlMF.TracksDebugUserValues)
-    MF.getProperties().set(
-        MachineFunctionProperties::Property::TracksDebugUserValues);
+    Props.setTracksDebugUserValues();
 
   PerFunctionMIParsingState PFS(MF, SM, IRSlots, *Target);
   if (parseRegisterInfo(PFS, YamlMF))
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 906048679553c..f50d42c59a81f 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -209,25 +209,16 @@ void MIRPrinter::print(const MachineFunction &MF) {
   YamlMF.IsOutlined = MF.isOutlined();
   YamlMF.UseDebugInstrRef = MF.useDebugInstrRef();
 
-  YamlMF.Legalized = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::Legalized);
-  YamlMF.RegBankSelected = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::RegBankSelected);
-  YamlMF.Selected = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::Selected);
-  YamlMF.FailedISel = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::FailedISel);
-  YamlMF.FailsVerification = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::FailsVerification);
-  YamlMF.TracksDebugUserValues = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::TracksDebugUserValues);
-
-  YamlMF.NoPHIs = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::NoPHIs);
-  YamlMF.IsSSA = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::IsSSA);
-  YamlMF.NoVRegs = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::NoVRegs);
+  const MachineFunctionProperties &Props = MF.getProperties();
+  YamlMF.Legalized = Props.hasLegalized();
+  YamlMF.RegBankSelected = Props.hasRegBankSelected();
+  YamlMF.Selected = Props.hasSelected();
+  YamlMF.FailedISel = Props.hasFailedISel();
+  YamlMF.FailsVerification = Props.hasFailsVerification();
+  YamlMF.TracksDebugUserValues = Props.hasTracksDebugUserValues();
+  YamlMF.NoPHIs = Props.hasNoPHIs();
+  YamlMF.IsSSA = Props.hasIsSSA();
+  YamlMF.NoVRegs = Props.hasNoVRegs();
 
   convert(YamlMF, MF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   MachineModuleSlotTracker MST(MMI, &MF);
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 37fe37fd6e423..76227b774f89c 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1776,17 +1776,15 @@ void MachineBasicBlock::clearLiveIns(
 }
 
 MachineBasicBlock::livein_iterator MachineBasicBlock::livein_begin() const {
-  assert(getParent()->getProperties().hasProperty(
-      MachineFunctionProperties::Property::TracksLiveness) &&
-      "Liveness information is accurate");
+  assert(getParent()->getProperties().hasTracksLiveness() &&
+         "Liveness information is accurate");
   return LiveIns.begin();
 }
 
 MachineBasicBlock::liveout_iterator MachineBasicBlock::liveout_begin() const {
   const MachineFunction &MF = *getParent();
-  assert(MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::TracksLiveness) &&
-      "Liveness information is accurate");
+  assert(MF.getProperties().hasTracksLiveness() &&
+         "Liveness information is accurate");
 
   const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
   MCRegister ExceptionPointer, ExceptionSelector;
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index bebdead5ecb89..780ed92bc8581 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -153,8 +153,7 @@ class MachineCSELegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 } // end anonymous namespace
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 6eab87c1292e0..39980c39bd023 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -514,8 +514,7 @@ class MachineCopyPropagationLegacy : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index 833b765b14d35..607e87a38274b 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -187,8 +187,8 @@ void MachineFunction::handleChangeDesc(MachineInstr &MI,
 
 void MachineFunction::init() {
   // Assume the function starts in SSA form with correct liveness.
-  Properties.set(MachineFunctionProperties::Property::IsSSA);
-  Properties.set(MachineFunctionProperties::Property::TracksLiveness);
+  Properties.setIsSSA();
+  Properties.setTracksLiveness();
   RegInfo = new (Allocator) MachineRegisterInfo(this);
 
   MFInfo = nullptr;
diff --git a/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp b/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
index c8c8ed99d93ea..26b6f5af5c49b 100644
--- a/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
+++ b/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
@@ -81,8 +81,7 @@ class MachineLateInstrsCleanupLegacy : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 
diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp
index ba125d9fee566..e48612369a5db 100644
--- a/llvm/lib/CodeGen/MachineOutliner.cpp
+++ b/llvm/lib/CodeGen/MachineOutliner.cpp
@@ -962,10 +962,10 @@ MachineFunction *MachineOutliner::createOutlinedFunction(
     computeAndPublishHashSequence(MF, OF.Candidates.size());
 
   // Set normal properties for a late MachineFunction.
-  MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA);
-  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
-  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
-  MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
+  MF.getProperties().resetIsSSA();
+  MF.getProperties().setNoPHIs();
+  MF.getProperties().setNoVRegs();
+  MF.getProperties().setTracksLiveness();
   MF.getRegInfo().freezeReservedRegs();
 
   // Compute live-in set for outlined fn
@@ -1111,8 +1111,7 @@ bool MachineOutliner::outline(
       // anything we outline doesn't break liveness assumptions. The outlined
       // functions themselves currently don't track liveness, but we should
       // make sure that the ranges we yank things out of aren't wrong.
-      if (MBB.getParent()->getProperties().hasProperty(
-              MachineFunctionProperties::Property::TracksLiveness)) {
+      if (MBB.getParent()->getProperties().hasTracksLiveness()) {
         // The following code is to add implicit def operands to the call
         // instruction. It also updates call site information for moved
         // code.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index aa2987b6710a3..e3f6eda8ff065 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -2082,8 +2082,7 @@ class PostRAMachineSinking : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index a7dbceb88c4c8..109988246d0ab 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -383,8 +383,7 @@ struct MachineVerifierLegacyPass : public MachineFunctionPass {
     // Skip functions that have known verification problems.
     // FIXME: Remove this mechanism when all problematic passes have been
     // fixed.
-    if (MF.getProperties().hasProperty(
-            MachineFunctionProperties::Property::FailsVerification))
+    if (MF.getProperties().hasFailsVerification())
       return false;
 
     MachineVerifier(this, Banner.c_str(), &errs()).verify(MF);
@@ -400,8 +399,7 @@ MachineVerifierPass::run(MachineFunction &MF,
   // Skip functions that have known verification problems.
   // FIXME: Remove this mechanism when all problematic passes have been
   // fixed.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailsVerification))
+  if (MF.getProperties().hasFailsVerification())
     return PreservedAnalyses::all();
   MachineVerifier(MFAM, Banner.c_str(), &errs()).verify(MF);
   return PreservedAnalyses::all();
@@ -462,9 +460,7 @@ void MachineVerifier::verifyProperties(const MachineFunction &MF) {
   // If a pass has introduced virtual registers without clearing the
   // NoVRegs property (or set it without allocating the vregs)
   // then report an error.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::NoVRegs) &&
-      MRI->getNumVirtRegs())
+  if (MF.getProperties().hasNoVRegs() && MRI->getNumVirtRegs())
     report("Function has NoVRegs property but there are VReg operands", &MF);
 }
 
@@ -476,8 +472,8 @@ bool MachineVerifier::verify(const MachineFunction &MF) {
   RBI = MF.getSubtarget().getRegBankInfo();
   MRI = &MF.getRegInfo();
 
-  const bool isFunctionFailedISel = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::FailedISel);
+  const MachineFunctionProperties &Props = MF.getProperties();
+  const bool isFunctionFailedISel = Props.hasFailedISel();
 
   // If we're mid-GlobalISel and we already triggered the fallback path then
   // it's expected that the MIR is somewhat broken but that's ok since we'll
@@ -485,12 +481,9 @@ bool MachineVerifier::verify(const MachineFunction &MF) {
   if (isFunctionFailedISel)
     return true;
 
-  isFunctionRegBankSelected = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::RegBankSelected);
-  isFunctionSelected = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::Selected);
-  isFunctionTracksDebugUserValues = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::TracksDebugUserValues);
+  isFunctionRegBankSelected = Props.hasRegBankSelected();
+  isFunctionSelected = Props.hasSelected();
+  isFunctionTracksDebugUserValues = Props.hasTracksDebugUserValues();
 
   if (PASS) {
     auto *LISWrapper = PASS->getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
@@ -731,8 +724,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
   FirstTerminator = nullptr;
   FirstNonPHI = nullptr;
 
-  if (!MF->getProperties().hasProperty(
-      MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
+  if (!MF->getProperties().hasNoPHIs() && MRI->tracksLiveness()) {
     // If this block has allocatable physical registers live-in, check that
     // it is an entry block or landing pad.
     for (const auto &LI : MBB->liveins()) {
@@ -2285,8 +2277,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     report("NoConvergent flag expected only on convergent instructions.", MI);
 
   if (MI->isPHI()) {
-    if (MF->getProperties().hasProperty(
-            MachineFunctionProperties::Property::NoPHIs))
+    if (MF->getProperties().hasNoPHIs())
       report("Found PHI instruction with NoPHIs property set", MI);
 
     if (FirstNonPHI)
@@ -2303,9 +2294,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
       report("Unspillable Terminator does not define a reg", MI);
     Register Def = MI->getOperand(0).getReg();
-    if (Def.isVirtual() &&
-        !MF->getProperties().hasProperty(
-            MachineFunctionProperties::Property::NoPHIs) &&
+    if (Def.isVirtual() && !MF->getProperties().hasNoPHIs() &&
         std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
       report("Unspillable Terminator expected to have at most one use!", MI);
   }
@@ -2626,9 +2615,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
     // TiedOpsRewritten property to verify two-address constraints, this
     // property will be set in twoaddressinstruction pass.
     unsigned DefIdx;
-    if (MF->getProperties().hasProperty(
-            MachineFunctionProperties::Property::TiedOpsRewritten) &&
-        MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
+    if (MF->getProperties().hasTiedOpsRewritten() && MO->isUse() &&
+        MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
         Reg != MI->getOperand(DefIdx).getReg())
       report("Two-address instruction operands must be identical", MO, MONum);
 
@@ -3729,9 +3717,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
     // early-clobber slot if it is being redefined by an early-clobber def.
     // TODO: Before tied operands are rewritten, a live segment can only end at
     // an early-clobber slot if the last use is tied to an early-clobber def.
-    if (MF->getProperties().hasProperty(
-            MachineFunctionProperties::Property::TiedOpsRewritten) &&
-        S.end.isEarlyClobber()) {
+    if (MF->getProperties().hasTiedOpsRewritten() && S.end.isEarlyClobber()) {
       if (I + 1 == LR.end() || (I + 1)->start != S.end) {
         report("Live segment ending at early clobber slot must be "
                "redefined by an EC def in the same instruction",
diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp
index 14f91a87f75b4..a93a89ecaa96e 100644
--- a/llvm/lib/CodeGen/PHIElimination.cpp
+++ b/llvm/lib/CodeGen/PHIElimination.cpp
@@ -152,8 +152,7 @@ class PHIElimination : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getSetProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
@@ -285,7 +284,7 @@ bool PHIEliminationImpl::run(MachineFunction &MF) {
   ImpDefs.clear();
   VRegPHIUseCount.clear();
 
-  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+  MF.getProperties().setNoPHIs();
 
   return Changed;
 }
diff --git a/llvm/lib/CodeGen/PatchableFunction.cpp b/llvm/lib/CodeGen/PatchableFunction.cpp
index 07e6c1d90e786..405b9fd3388c8 100644
--- a/llvm/lib/CodeGen/PatchableFunction.cpp
+++ b/llvm/lib/CodeGen/PatchableFunction.cpp
@@ -38,8 +38,7 @@ struct PatchableFunctionLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 27b22e68d919e..81f14a4cca055 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -577,8 +577,7 @@ class PeepholeOptimizerLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp
index 039a473382732..06e5b18c19301 100644
--- a/llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -106,8 +106,7 @@ class PostRASchedulerLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
index be81ecab9c897..6c84cc2b64324 100644
--- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
+++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
@@ -48,8 +48,7 @@ class ProcessImplicitDefs : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 } // end anonymous namespace
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 961b2f055f026..7b149cf901ca8 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -659,8 +659,7 @@ void PEIImpl::spillCalleeSavedRegs(MachineFunction &MF) {
   // pipeline is set up without giving the passes a chance to look at the
   // TargetMachine.
   // FIXME: Find a way to express this in getRequiredProperties.
-  assert(MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::NoVRegs));
+  assert(MF.getProperties().hasNoVRegs());
 
   const Function &F = MF.getFunction();
   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp
index b9599e77fbf0a..69b92917399fd 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -216,10 +216,9 @@ MCPhysReg RegAllocBase::getErrorAssignment(const TargetRegisterClass &RC,
 
   // Avoid printing the error for every single instance of the register. It
   // would be better if this were per register class.
-  bool EmitError = !MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::FailedRegAlloc);
+  bool EmitError = !MF.getProperties().hasFailedRegAlloc();
   if (EmitError)
-    MF.getProperties().set(MachineFunctionProperties::Property::FailedRegAlloc);
+    MF.getProperties().setFailedRegAlloc();
 
   const Function &Fn = MF.getFunction();
   LLVMContext &Context = Fn.getContext();
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index 51e047b2fa3f0..381249ec8371a 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -105,13 +105,11 @@ class RABasic : public MachineFunctionPass,
   bool runOnMachineFunction(MachineFunction &mf) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-      MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   // Helper for spilling all live virtual registers currently unified under preg
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index bb118dd9e1867..66a206c9b2344 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -417,22 +417,19 @@ class RegAllocFast : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 
   MachineFunctionProperties getSetProperties() const override {
     if (Impl.ClearVirtRegs) {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     return MachineFunctionProperties();
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 
@@ -1196,10 +1193,9 @@ MCPhysReg RegAllocFastImpl::getErrorAssignment(const LiveReg &LR,
   MachineFunction &MF = *MI.getMF();
 
   // Avoid repeating the error every time a register is used.
-  bool EmitError = !MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::FailedRegAlloc);
+  bool EmitError = !MF.getProperties().hasFailedRegAlloc();
   if (EmitError)
-    MF.getProperties().set(MachineFunctionProperties::Property::FailedRegAlloc);
+    MF.getProperties().setFailedRegAlloc();
 
   // If the allocation order was empty, all registers in the class were
   // probably reserved. Fall back to taking the first register in the class,
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index c93848022c04d..fa384b296f2e6 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -158,13 +158,11 @@ class RAGreedyLegacy : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &mf) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index e230a1be95c9f..048cd21db062d 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -135,13 +135,11 @@ class RegAllocPBQP : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-      MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
 private:
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index c27435aa2dae0..2d25f097348af 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -398,8 +398,7 @@ class RegisterCoalescerLegacy : public MachineFunctionPass {
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   /// This is the pass entry point.
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index f5bc9021eea15..7e26c2ed59949 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -467,7 +467,7 @@ void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {
   MachineRegisterInfo &MRI = MF.getRegInfo();
   // Shortcut.
   if (MRI.getNumVirtRegs() == 0) {
-    MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
+    MF.getProperties().setNoVRegs();
     return;
   }
 
@@ -489,7 +489,7 @@ void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {
   }
 
   MRI.clearVirtRegs();
-  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
+  MF.getProperties().setNoVRegs();
 }
 
 namespace {
diff --git a/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp b/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
index 0c05473c7449b..ea0ea0221a4f8 100644
--- a/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
+++ b/llvm/lib/CodeGen/RemoveLoadsIntoFakeUses.cpp
@@ -58,8 +58,7 @@ class RemoveLoadsIntoFakeUsesLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override {
diff --git a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp
index 0cebad42c0ff8..4a0ceed984f61 100644
--- a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp
+++ b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp
@@ -60,8 +60,7 @@ namespace {
       auto ClearVRegTypesOnReturn =
           make_scope_exit([&MF]() { MF.getRegInfo().clearVirtRegTypes(); });
 
-      if (MF.getProperties().hasProperty(
-              MachineFunctionProperties::Property::FailedISel)) {
+      if (MF.getProperties().hasFailedISel()) {
         if (AbortOnFailedISel)
           report_fatal_error("Instruction selection failed");
         LLVM_DEBUG(dbgs() << "Resetting: " << MF.getName() << '\n');
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 1bc30336a02bf..802c6b54cec5c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -345,8 +345,7 @@ SelectionDAGISelLegacy::SelectionDAGISelLegacy(
 
 bool SelectionDAGISelLegacy::runOnMachineFunction(MachineFunction &MF) {
   // If we already selected that function, we do not need to run SDISel.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::Selected))
+  if (MF.getProperties().hasSelected())
     return false;
 
   // Do some sanity-checking on the command-line options.
@@ -421,8 +420,7 @@ PreservedAnalyses
 SelectionDAGISelPass::run(MachineFunction &MF,
                           MachineFunctionAnalysisManager &MFAM) {
   // If we already selected that function, we do not need to run SDISel.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::Selected))
+  if (MF.getProperties().hasSelected())
     return PreservedAnalyses::all();
 
   // Do some sanity-checking on the command-line options.
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index 1781e622e780e..41e956caa7b34 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -275,8 +275,7 @@ class ShrinkWrapLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-      MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override { return "Shrink Wrapping analysis"; }
diff --git a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
index 8437422843147..462d9e0f4cf48 100644
--- a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
+++ b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
@@ -62,8 +62,7 @@ class StackMapLiveness : public MachineFunctionPass {
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   /// Calculate the liveness information for the given machine function.
diff --git a/llvm/lib/CodeGen/TailDuplication.cpp b/llvm/lib/CodeGen/TailDuplication.cpp
index a50cdcfa7cc60..bcec318a85409 100644
--- a/llvm/lib/CodeGen/TailDuplication.cpp
+++ b/llvm/lib/CodeGen/TailDuplication.cpp
@@ -66,8 +66,7 @@ class EarlyTailDuplicateLegacy : public TailDuplicateBaseLegacy {
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties()
-      .set(MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 };
 
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 3e29f62005478..8b82deb2a9d83 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1846,8 +1846,7 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
 
   // To simplify the sub-register handling, verify that we only need to
   // consider physical registers.
-  assert(MF->getProperties().hasProperty(
-      MachineFunctionProperties::Property::NoVRegs));
+  assert(MF->getProperties().hasNoVRegs());
 
   if (auto DestSrc = isCopyInstr(MI)) {
     Register DestReg = DestSrc->Destination->getReg();
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 36e2156165f49..8d94b40a41bea 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1837,8 +1837,7 @@ bool TwoAddressInstructionImpl::run() {
   MRI->leaveSSA();
 
   // This pass will rewrite the tied-def to meet the RegConstraint.
-  MF->getProperties()
-      .set(MachineFunctionProperties::Property::TiedOpsRewritten);
+  MF->getProperties().setTiedOpsRewritten();
 
   TiedOperandMap TiedOperands;
   for (MachineBasicBlock &MBBI : *MF) {
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 49e819e2d10f7..3d6ccba894e9c 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -244,8 +244,7 @@ class VirtRegRewriterLegacy : public MachineFunctionPass {
 
   MachineFunctionProperties getSetProperties() const override {
     if (ClearVirtRegs) {
-      return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     return MachineFunctionProperties();



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