[llvm] [RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (PR #139840)

[Sam Elliott via llvm-commits]

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@@ -734,38 +734,42 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
 ; RV32IZFINXZDINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI12_0)
+; RV32IZFINXZDINX-NEXT:    lw a4, %lo(.LCPI12_0)(a2)
+; RV32IZFINXZDINX-NEXT:    addi a2, a2, %lo(.LCPI12_0)
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lenary wrote:

I think there has been discussion in the scalar efficiency sig about when clang/llvm uses constant pools for e.g. 64-bit integers - Zilsd may be another place to revisit whether those should be split before materialization, or put in a constant pool and loaded with `ld`. https://lists.riscv.org/g/sig-scalar-efficiency/topic/110801992 is the discussion, which I note does focus more on 48-bit instructions for materialisation rather than constant pools.

https://github.com/llvm/llvm-project/pull/139840