[llvm] [RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (PR #139840)

[Craig Topper via llvm-commits]

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@@ -734,38 +734,42 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
 ; RV32IZFINXZDINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI12_0)
+; RV32IZFINXZDINX-NEXT:    lw a4, %lo(.LCPI12_0)(a2)
+; RV32IZFINXZDINX-NEXT:    addi a2, a2, %lo(.LCPI12_0)
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topperc wrote:

Yes. I have a patch I'll post later. It only affected the Zdinx lit tests from this patch. Let me know if you have any suggestions on how to hit this issue outside of Zdinx.

https://github.com/llvm/llvm-project/pull/139840