[llvm] [SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (PR #139930)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 14 09:47:02 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-sparc
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
This matches the underlying function in MachineMemOperand and how it is printed when BaseAlign differs from Align.
---
Patch is 73.43 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/139930.diff
14 Files Affected:
- (modified) llvm/include/llvm/CodeGen/SelectionDAGNodes.h (+1-1)
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+19-20)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (+18-19)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (+6-6)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (+12-12)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (+8-9)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+23-25)
- (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+20-24)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+9-9)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+7-8)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+8-9)
- (modified) llvm/lib/Target/Sparc/SparcISelLowering.cpp (+5-7)
- (modified) llvm/lib/Target/SystemZ/SystemZISelLowering.cpp (+14-18)
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+49-62)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index cfefceea8f0fe..1a373f4c10e78 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -1386,7 +1386,7 @@ class MemSDNode : public SDNode {
bool writeMem() const { return MMO->isStore(); }
/// Returns alignment and volatility of the memory access
- Align getOriginalAlign() const { return MMO->getBaseAlign(); }
+ Align getBaseAlign() const { return MMO->getBaseAlign(); }
Align getAlign() const { return MMO->getAlign(); }
/// Return the SubclassData value, without HasDebugValue. This contains an
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d6e288a59b2ee..64a1fd07c57ca 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12377,8 +12377,8 @@ SDValue DAGCombiner::visitMSTORE(SDNode *N) {
!MST->isCompressingStore() && !MST->isTruncatingStore())
return DAG.getStore(MST->getChain(), SDLoc(N), MST->getValue(),
MST->getBasePtr(), MST->getPointerInfo(),
- MST->getOriginalAlign(),
- MST->getMemOperand()->getFlags(), MST->getAAInfo());
+ MST->getBaseAlign(), MST->getMemOperand()->getFlags(),
+ MST->getAAInfo());
// Try transforming N to an indexed store.
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
@@ -12562,7 +12562,7 @@ SDValue DAGCombiner::visitMLOAD(SDNode *N) {
!MLD->isExpandingLoad() && MLD->getExtensionType() == ISD::NON_EXTLOAD) {
SDValue NewLd = DAG.getLoad(
N->getValueType(0), SDLoc(N), MLD->getChain(), MLD->getBasePtr(),
- MLD->getPointerInfo(), MLD->getOriginalAlign(),
+ MLD->getPointerInfo(), MLD->getBaseAlign(),
MLD->getMemOperand()->getFlags(), MLD->getAAInfo(), MLD->getRanges());
return CombineTo(N, NewLd, NewLd.getValue(1));
}
@@ -13602,7 +13602,7 @@ SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
SDValue SplitLoad =
DAG.getExtLoad(ExtType, SDLoc(LN0), SplitDstVT, LN0->getChain(),
BasePtr, LN0->getPointerInfo().getWithOffset(Offset),
- SplitSrcVT, LN0->getOriginalAlign(),
+ SplitSrcVT, LN0->getBaseAlign(),
LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
BasePtr = DAG.getMemBasePlusOffset(BasePtr, TypeSize::getFixed(Stride), DL);
@@ -15159,15 +15159,15 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
} else if (CR.getBitWidth() == BitSize)
NewRanges = OldRanges;
}
- Load = DAG.getLoad(
- VT, DL, LN0->getChain(), NewPtr,
- LN0->getPointerInfo().getWithOffset(PtrOff), LN0->getOriginalAlign(),
- LN0->getMemOperand()->getFlags(), LN0->getAAInfo(), NewRanges);
+ Load = DAG.getLoad(VT, DL, LN0->getChain(), NewPtr,
+ LN0->getPointerInfo().getWithOffset(PtrOff),
+ LN0->getBaseAlign(), LN0->getMemOperand()->getFlags(),
+ LN0->getAAInfo(), NewRanges);
} else
Load = DAG.getExtLoad(ExtType, DL, VT, LN0->getChain(), NewPtr,
LN0->getPointerInfo().getWithOffset(PtrOff), ExtVT,
- LN0->getOriginalAlign(),
- LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
+ LN0->getBaseAlign(), LN0->getMemOperand()->getFlags(),
+ LN0->getAAInfo());
// Replace the old load's chain with the new load's chain.
WorklistRemover DeadNodes(*this);
@@ -20583,16 +20583,15 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
++OpsNarrowed;
if (UseTruncStore)
return DAG.getTruncStore(St->getChain(), SDLoc(St), IVal, Ptr,
- St->getPointerInfo().getWithOffset(StOffset),
- VT, St->getOriginalAlign());
+ St->getPointerInfo().getWithOffset(StOffset), VT,
+ St->getBaseAlign());
// Truncate down to the new size.
IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
- return DAG
- .getStore(St->getChain(), SDLoc(St), IVal, Ptr,
- St->getPointerInfo().getWithOffset(StOffset),
- St->getOriginalAlign());
+ return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
+ St->getPointerInfo().getWithOffset(StOffset),
+ St->getBaseAlign());
}
/// Look for sequence of load / op / store where op is one of 'or', 'xor', and
@@ -22113,11 +22112,11 @@ SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) {
AAMDNodes AAInfo = ST->getAAInfo();
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(4), DL);
SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr,
ST->getPointerInfo().getWithOffset(4),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
St0, St1);
}
@@ -22588,13 +22587,13 @@ SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
SDValue Ptr = ST->getBasePtr();
// Lower value store.
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
Ptr =
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(HalfValBitSize / 8), DL);
// Higher value store.
SDValue St1 = DAG.getStore(
St0, DL, Hi, Ptr, ST->getPointerInfo().getWithOffset(HalfValBitSize / 8),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
return St1;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 3e47136edbefc..528c07cc5549d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -441,7 +441,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
bitcastToAPInt().zextOrTrunc(32),
SDLoc(CFP), MVT::i32);
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
}
if (CFP->getValueType(0) == MVT::f64 &&
@@ -451,7 +451,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
zextOrTrunc(64), SDLoc(CFP), MVT::i64);
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
}
if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
@@ -465,11 +465,11 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
std::swap(Lo, Hi);
Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(4), dl);
Hi = DAG.getStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(4),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
@@ -525,7 +525,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
"Can only promote stores to same size type");
Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
SDValue Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
ReplaceNode(SDValue(Node, 0), Result);
break;
}
@@ -548,7 +548,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
Value = DAG.getZeroExtendInReg(Value, dl, StVT);
SDValue Result =
DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
ReplaceNode(SDValue(Node, 0), Result);
} else if (!StVT.isVector() && !isPowerOf2_64(StWidth.getFixedValue())) {
// If not storing a power-of-2 number of bits, expand as two stores.
@@ -571,7 +571,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE at +2:i8 (srl X, 16)
// Store the bottom RoundWidth bits.
Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
- RoundVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
+ RoundVT, ST->getBaseAlign(), MMOFlags, AAInfo);
// Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
@@ -583,7 +583,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
TLI.getShiftAmountTy(Value.getValueType(), DL)));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize),
- ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
} else {
// Big endian - avoid unaligned stores.
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE at +2:i8 X
@@ -593,7 +593,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
DAG.getConstant(ExtraWidth, dl,
TLI.getShiftAmountTy(Value.getValueType(), DL)));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), RoundVT,
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
// Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
@@ -602,7 +602,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
Ptr.getValueType()));
Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize),
- ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
}
// The order of the stores doesn't matter.
@@ -638,16 +638,15 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
if (TLI.isTypeLegal(StVT)) {
Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
} else {
// The in-memory type isn't legal. Truncate to the type it would promote
// to, and then do a truncstore.
Value = DAG.getNode(ISD::TRUNCATE, dl,
TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
Value);
- Result =
- DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), StVT,
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
+ StVT, ST->getBaseAlign(), MMOFlags, AAInfo);
}
ReplaceNode(SDValue(Node, 0), Result);
@@ -753,7 +752,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
SDValue Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
Chain, Ptr, LD->getPointerInfo(), NVT,
- LD->getOriginalAlign(), MMOFlags, AAInfo);
+ LD->getBaseAlign(), MMOFlags, AAInfo);
Ch = Result.getValue(1); // The chain.
@@ -792,7 +791,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD at +2:i8, 16)
// Load the bottom RoundWidth bits.
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
- LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
+ LD->getPointerInfo(), RoundVT, LD->getBaseAlign(),
MMOFlags, AAInfo);
// Load the remaining ExtraWidth bits.
@@ -801,7 +800,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize),
- ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
+ ExtraVT, LD->getBaseAlign(), MMOFlags, AAInfo);
// Build a factor node to remember that this load is independent of
// the other one.
@@ -821,7 +820,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8
// Load the top RoundWidth bits.
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
- LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
+ LD->getPointerInfo(), RoundVT, LD->getBaseAlign(),
MMOFlags, AAInfo);
// Load the remaining ExtraWidth bits.
@@ -830,7 +829,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize),
- ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
+ ExtraVT, LD->getBaseAlign(), MMOFlags, AAInfo);
// Build a factor node to remember that this load is independent of
// the other one.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 432209e8ecb0a..07470d58f09d7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -967,8 +967,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
if (L->getExtensionType() == ISD::NON_EXTLOAD) {
NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
L->getChain(), L->getBasePtr(), L->getOffset(),
- L->getPointerInfo(), NVT, L->getOriginalAlign(),
- MMOFlags, L->getAAInfo());
+ L->getPointerInfo(), NVT, L->getBaseAlign(), MMOFlags,
+ L->getAAInfo());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
@@ -978,8 +978,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
// Do a non-extending load followed by FP_EXTEND.
NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(),
dl, L->getChain(), L->getBasePtr(), L->getOffset(),
- L->getPointerInfo(), L->getMemoryVT(),
- L->getOriginalAlign(), MMOFlags, L->getAAInfo());
+ L->getPointerInfo(), L->getMemoryVT(), L->getBaseAlign(),
+ MMOFlags, L->getAAInfo());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
@@ -3105,7 +3105,7 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) {
SDValue newL = DAG.getLoad(
L->getAddressingMode(), L->getExtensionType(), IVT, SDLoc(N),
L->getChain(), L->getBasePtr(), L->getOffset(), L->getPointerInfo(), IVT,
- L->getOriginalAlign(), L->getMemOperand()->getFlags(), L->getAAInfo());
+ L->getBaseAlign(), L->getMemOperand()->getFlags(), L->getAAInfo());
// Legalize the chain result by replacing uses of the old value chain with the
// new one
ReplaceValueWith(SDValue(N, 1), newL.getValue(1));
@@ -3531,7 +3531,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_LOAD(SDNode *N) {
SDValue NewL =
DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), MVT::i16,
SDLoc(N), L->getChain(), L->getBasePtr(), L->getOffset(),
- L->getPointerInfo(), MVT::i16, L->getOriginalAlign(),
+ L->getPointerInfo(), MVT::i16, L->getBaseAlign(),
L->getMemOperand()->getFlags(), L->getAAInfo());
// Legalize the chain result by replacing uses of the old value chain with the
// new one
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 25e74a2ae5b71..73c1c49041766 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -4249,7 +4249,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
EVT MemVT = N->getMemoryVT();
Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ N->getBaseAlign(), MMOFlags, AAInfo);
// Remember the chain.
Ch = Lo.getValue(1);
@@ -4271,8 +4271,8 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
}
} else if (DAG.getDataLayout().isLittleEndian()) {
// Little-endian - low bits are at low addresses.
- Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), N->getBaseAlign(),
+ MMOFlags, AAInfo);
unsigned ExcessBits =
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
@@ -4283,7 +4283,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ N->getBaseAlign(), MMOFlags, AAInfo);
// Build a factor node to remember that this load is independent of the
// other one.
@@ -4301,7 +4301,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
EVT::getIntegerVT(*DAG.getContext(),
MemVT.getSizeInBits() - ExcessBits),
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ N->getBaseAlign(), MMOFlags, AAInfo);
// Increment the pointer to the other half.
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
@@ -4309,7 +4309,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
N->getPointerInfo().getWithOffset(Increment...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/139930
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