[llvm] [RISCV] Lower i64 load/stores to ld/sd with Zilsd. (PR #139808)

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 97eabe6e0..04dcbfdc3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7769,7 +7769,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, StoredVal,
                                DAG.getTargetConstant(1, DL, MVT::i32));
 
-     return DAG.getMemIntrinsicNode(
+      return DAG.getMemIntrinsicNode(
           RISCVISD::SD_RV32, DL, DAG.getVTList(MVT::Other),
           {Store->getChain(), Lo, Hi, Store->getBasePtr()}, MVT::i64,
           Store->getMemOperand());

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https://github.com/llvm/llvm-project/pull/139808