[llvm] [RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (PR #139840)

[Philip Reames via llvm-commits]

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@@ -7705,19 +7710,42 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   }
   case ISD::LOAD: {
     auto *Load = cast<LoadSDNode>(Op);
-    EVT VecTy = Load->getMemoryVT();
+    EVT VT = Load->getValueType(0);
+    if (VT == MVT::f64) {
+      assert(Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit() &&
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preames wrote:

So, this is an off topic pondering.  For Zdinx and friends, what happens if we custom legalize all the FP loads and stores into their corresponding integer types?  We can't declare the type illegal, but would making the operations illegal work out?  There would be two rounds of legalization 1) FP64 -> I64, 2) I64 -> split i32.  Would that work out?

https://github.com/llvm/llvm-project/pull/139840