[llvm] [RISCV] Change type of Zicbop prefetch operand to GPRMem (PR #139888)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Alexander Romanov (arrv-sc)

<details>
<summary>Changes</summary>

Prior to this commit PREFETCH_* instructions considered their operand register to be a simple GPR which is not entirely correct as it is a base address for possible prefetching operation (According to cmobase v1.0.1)

---
Full diff: https://github.com/llvm/llvm-project/pull/139888.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
index 56c870414596b..e44bdcb4e2f0f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
@@ -37,7 +37,7 @@ class CBO_r<bits<12> optype, string opcodestr>
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
 class Prefetch_ri<bits<5> optype, string opcodestr>
-    : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPR:$rs1, simm12_lsb00000:$imm12),
+    : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPRMem:$rs1, simm12_lsb00000:$imm12),
               opcodestr, "${imm12}(${rs1})"> {
   let Inst{11-7} = 0b00000;
   let rs2 = optype;

``````````

</details>


https://github.com/llvm/llvm-project/pull/139888