[llvm] [SelectionDAG] Add an ISD node for for get.active.lane.mask (PR #139084)

[Kerry McLaughlin via llvm-commits]

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@@ -18142,6 +18130,70 @@ static SDValue performVecReduceAddCombineWithUADDLP(SDNode *N,
   return DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i32, UADDLP);
 }
 
+static SDValue
+performActiveLaneMaskCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
+                             const AArch64Subtarget *ST) {
+  if (SDValue While = optimizeIncrementingWhile(N, DCI.DAG, /*IsSigned=*/false,
+                                                /*IsEqual=*/false))
+    return While;
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kmclaughlin-arm wrote:

The only other difference is that I changed the operand numbers passed to N->getOperand() later to set `Idx` & `TC`, as this now operates on the ISD node rather than the whilelo intrinsic. Otherwise this is identical to `tryCombineWhileLo`.

https://github.com/llvm/llvm-project/pull/139084