[llvm] 2070044 - [LLVM][AArch64] Set hasAndNot() to true for scalable vectors. (#139755)

[via llvm-commits]

Author: Paul Walker
Date: 2025-05-14T12:04:20+01:00
New Revision: 2070044c17242ad290665dc46bac5cd1c2b5e2c1

URL: https://github.com/llvm/llvm-project/commit/2070044c17242ad290665dc46bac5cd1c2b5e2c1
DIFF: https://github.com/llvm/llvm-project/commit/2070044c17242ad290665dc46bac5cd1c2b5e2c1.diff

LOG: [LLVM][AArch64] Set hasAndNot() to true for scalable vectors. (#139755)

NOTE: I've not added an SVE check because the use of scalable vectors
implies SVE or StreamingSVE must be available.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.h
    llvm/test/CodeGen/AArch64/sve2-bsl.ll
    llvm/test/CodeGen/AArch64/vselect-constants.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 9d8d1c22258be..ec8b0b920c453 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -875,9 +875,10 @@ class AArch64TargetLowering : public TargetLowering {
     if (!VT.isVector())
       return hasAndNotCompare(Y);
 
-    TypeSize TS = VT.getSizeInBits();
-    // TODO: We should be able to use bic/bif too for SVE.
-    return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
+    if (VT.isScalableVector())
+      return true;
+
+    return VT.getFixedSizeInBits() >= 64; // vector 'bic'
   }
 
   bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(

diff  --git a/llvm/test/CodeGen/AArch64/sve2-bsl.ll b/llvm/test/CodeGen/AArch64/sve2-bsl.ll
index e524c5d6b453e..8aedeac18f64a 100644
--- a/llvm/test/CodeGen/AArch64/sve2-bsl.ll
+++ b/llvm/test/CodeGen/AArch64/sve2-bsl.ll
@@ -299,3 +299,16 @@ define <vscale x 2 x i64> @codegen_bsl2n_i64(<vscale x 2 x i64> %0, <vscale x 2
   %7 = or <vscale x 2 x i64> %4, %6
   ret <vscale x 2 x i64> %7
 }
+
+; (A ^ B) & C) ^ B -> (A & C) | (B & !C) when BIC instructions are available.
+define <vscale x 4 x i32> @bsl_combine_when_bic_available(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
+; CHECK-LABEL: bsl_combine_when_bic_available:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    bsl z0.d, z0.d, z1.d, z2.d
+; CHECK-NEXT:    ret
+entry:
+  %t1 = xor <vscale x 4 x i32> %a, %b
+  %t2 = and <vscale x 4 x i32> %t1, %c
+  %t3 = xor <vscale x 4 x i32> %t2, %b
+  ret <vscale x 4 x i32> %t3
+}

diff  --git a/llvm/test/CodeGen/AArch64/vselect-constants.ll b/llvm/test/CodeGen/AArch64/vselect-constants.ll
index 5e6ff1e0740ce..a7cf5ece5d270 100644
--- a/llvm/test/CodeGen/AArch64/vselect-constants.ll
+++ b/llvm/test/CodeGen/AArch64/vselect-constants.ll
@@ -369,10 +369,9 @@ define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
 define <vscale x 16 x i8> @signbit_mask_xor_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
 ; CHECK-LABEL: signbit_mask_xor_nxv16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    cmplt p0.b, p0/z, z0.b, #0
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
-; CHECK-NEXT:    mov z0.b, p0/m, #0 // =0x0
+; CHECK-NEXT:    eor z1.d, z0.d, z1.d
+; CHECK-NEXT:    asr z0.b, z0.b, #7
+; CHECK-NEXT:    bic z0.d, z1.d, z0.d
 ; CHECK-NEXT:    ret
   %cond = icmp slt <vscale x 16 x i8> %a, zeroinitializer
   %xor = xor <vscale x 16 x i8> %a, %b