[llvm] 82b179c - [RISCV][VLOPT] Consider EMUL if it is unknown in EMULAndEEWAreEqual (#139670)

[via llvm-commits]

Author: Piyou Chen
Date: 2025-05-14T18:03:35+08:00
New Revision: 82b179ca6621f2f0b7bc6062fddb1af663785041

URL: https://github.com/llvm/llvm-project/commit/82b179ca6621f2f0b7bc6062fddb1af663785041
DIFF: https://github.com/llvm/llvm-project/commit/82b179ca6621f2f0b7bc6062fddb1af663785041.diff

LOG: [RISCV][VLOPT] Consider EMUL if it is unknown in EMULAndEEWAreEqual (#139670)

Fix https://github.com/llvm/llvm-project/issues/139288

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
    llvm/test/CodeGen/RISCV/rvv/vl-opt.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 9ed2ba274bc53..f7cbfa1546de6 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -83,8 +83,7 @@ struct OperandInfo {
   OperandInfo() = delete;
 
   static bool EMULAndEEWAreEqual(const OperandInfo &A, const OperandInfo &B) {
-    return A.Log2EEW == B.Log2EEW && A.EMUL->first == B.EMUL->first &&
-           A.EMUL->second == B.EMUL->second;
+    return A.Log2EEW == B.Log2EEW && A.EMUL == B.EMUL;
   }
 
   static bool EEWAreEqual(const OperandInfo &A, const OperandInfo &B) {

diff  --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index 6343afc6bac62..988335126e62e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -498,4 +498,29 @@ body: |
     %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
     PseudoBR %bb.1
 ...
+---
+name: EMUL_is_unknown
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    ; CHECK-LABEL: name: EMUL_is_unknown
+    ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 1, 0 /* e8 */
+    ; CHECK-NEXT: [[PseudoVMOR_MM_B4_:%[0-9]+]]:vmv0 = PseudoVMOR_MM_B4 [[PseudoVMCLR_M_B4_]], [[PseudoVMCLR_M_B4_]], 1, 0 /* e8 */
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+    ; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X $noreg, [[COPY]], 1, 5 /* e32 */
+    ; CHECK-NEXT: [[PseudoVMV_V_I_M8_:%[0-9]+]]:vrm8 = PseudoVMV_V_I_M8 $noreg, 0, 1, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: [[PseudoVREDMAX_VS_M8_E32_MASK:%[0-9]+]]:vrnov0 = PseudoVREDMAX_VS_M8_E32_MASK $noreg, killed [[PseudoVMV_V_I_M8_]], killed [[PseudoVMV_S_X]], [[PseudoVMOR_MM_B4_]], 1, 5 /* e32 */, 1 /* ta, mu */
+    ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S killed [[PseudoVREDMAX_VS_M8_E32_MASK]], 5 /* e32 */
+    ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %2:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+    %3:vmv0 = PseudoVMOR_MM_B4 %2, %2, 1, 0 /* e8 */
+    %4:gpr = COPY $x0
+    %5:vr = PseudoVMV_S_X $noreg, %4, 1, 5 /* e32 */
+    %6:vrm8 = PseudoVMV_V_I_M8 $noreg, 0, 1, 5 /* e32 */, 0 /* tu, mu */
+    %7:vrnov0 = PseudoVREDMAX_VS_M8_E32_MASK $noreg, killed %6, killed %5, %3, 1, 5 /* e32 */, 1 /* ta, mu */
+    %9:gpr = PseudoVMV_X_S killed %7, 5 /* e32 */
+    $x10 = COPY %9
+    PseudoRET implicit $x10
+...