[llvm] [AMDGPU] Handled G_UBSANTRAP GlobalIsel (PR #134492)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 14 01:39:36 PDT 2025
https://github.com/amansharma612 updated https://github.com/llvm/llvm-project/pull/134492
>From 515510f1ef088d2ed972d4b00e5660e207bb55b0 Mon Sep 17 00:00:00 2001
From: Aman Sharma <210100011 at iitb.ac.in>
Date: Sat, 5 Apr 2025 16:02:22 +0530
Subject: [PATCH 1/6] [AMDGPU] Added G_UBSANTRAP GlobalISel
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 27 ++++++++++++++++++-
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 5 ++++
llvm/test/CodeGen/AMDGPU/ubsan_trap.ll | 7 +++++
3 files changed, 38 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/ubsan_trap.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 275d0193452a5..a317bf884c984 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2103,7 +2103,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder({G_MEMCPY, G_MEMCPY_INLINE, G_MEMMOVE, G_MEMSET})
.lower();
- getActionDefinitionsBuilder({G_TRAP, G_DEBUGTRAP}).custom();
+ getActionDefinitionsBuilder({G_TRAP, G_DEBUGTRAP, G_UBSANTRAP}).custom();
getActionDefinitionsBuilder({G_VASTART, G_VAARG, G_BRJT, G_JUMP_TABLE,
G_INDEXED_LOAD, G_INDEXED_SEXTLOAD,
@@ -2222,6 +2222,8 @@ bool AMDGPULegalizerInfo::legalizeCustom(
return legalizeTrap(MI, MRI, B);
case TargetOpcode::G_DEBUGTRAP:
return legalizeDebugTrap(MI, MRI, B);
+ case TargetOpcode::G_UBSANTRAP:
+ return legalizeUbsanTrap(MI, MRI, B);
default:
return false;
}
@@ -7045,6 +7047,29 @@ bool AMDGPULegalizerInfo::legalizeDebugTrap(MachineInstr &MI,
return true;
}
+
+bool AMDGPULegalizerInfo::legalizeUbsanTrap(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const {
+ // Is non-HSA path or trap-handler disabled? Then, report a warning
+ // accordingly
+ if (!ST.isTrapHandlerEnabled() ||
+ ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
+ DiagnosticInfoUnsupported NoTrap(B.getMF().getFunction(),
+ "ubsantrap handler not supported",
+ MI.getDebugLoc(), DS_Warning);
+ LLVMContext &Ctx = B.getMF().getFunction().getContext();
+ Ctx.diagnose(NoTrap);
+ } else {
+ // Insert trap instruction
+ B.buildInstr(AMDGPU::S_TRAP)
+ .addImm(static_cast<unsigned>(GCNSubtarget::TrapID::LLVMAMDHSATrap));
+ }
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(
MachineInstr &MI, MachineIRBuilder &B) const {
MachineRegisterInfo &MRI = *B.getMRI();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 1f4e02b0d600a..5b775b3ef4a10 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -244,6 +244,11 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeDebugTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
+
+ bool legalizeUbsanTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const;
+
+
bool legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const override;
};
diff --git a/llvm/test/CodeGen/AMDGPU/ubsan_trap.ll b/llvm/test/CodeGen/AMDGPU/ubsan_trap.ll
new file mode 100644
index 0000000000000..9f961031a1ddb
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/ubsan_trap.ll
@@ -0,0 +1,7 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel < %s
+; LLVM ERROR: cannot select: G_UBSANTRAP 0 (in function: ubsan_trap)
+
+define void @ubsan_trap() {
+ call void @llvm.ubsantrap(i8 0)
+ ret void
+}
\ No newline at end of file
>From b92d165e1defdff6e019da9cbe69e12d3241c2c0 Mon Sep 17 00:00:00 2001
From: Aman Sharma <210100011 at iitb.ac.in>
Date: Sat, 5 Apr 2025 16:04:26 +0530
Subject: [PATCH 2/6] added clang-format output
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 3 +-
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 4 +-
llvm/test/CodeGen/AMDGPU/trap-abis.ll | 129 ++++++++++++++++++
llvm/test/CodeGen/AMDGPU/trap.ll | 19 +++
llvm/test/CodeGen/AMDGPU/ubsan_trap.ll | 7 -
5 files changed, 150 insertions(+), 12 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/ubsan_trap.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index a317bf884c984..e6ebbe97c51ca 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -7047,7 +7047,6 @@ bool AMDGPULegalizerInfo::legalizeDebugTrap(MachineInstr &MI,
return true;
}
-
bool AMDGPULegalizerInfo::legalizeUbsanTrap(MachineInstr &MI,
MachineRegisterInfo &MRI,
MachineIRBuilder &B) const {
@@ -7058,7 +7057,7 @@ bool AMDGPULegalizerInfo::legalizeUbsanTrap(MachineInstr &MI,
DiagnosticInfoUnsupported NoTrap(B.getMF().getFunction(),
"ubsantrap handler not supported",
MI.getDebugLoc(), DS_Warning);
- LLVMContext &Ctx = B.getMF().getFunction().getContext();
+ LLVMContext &Ctx = B.getContext();
Ctx.diagnose(NoTrap);
} else {
// Insert trap instruction
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 5b775b3ef4a10..076a66bb6012f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -244,10 +244,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeDebugTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
-
bool legalizeUbsanTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const;
-
+ MachineIRBuilder &B) const;
bool legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const override;
diff --git a/llvm/test/CodeGen/AMDGPU/trap-abis.ll b/llvm/test/CodeGen/AMDGPU/trap-abis.ll
index b8f0d7617167e..dcdf9962d2ffe 100644
--- a/llvm/test/CodeGen/AMDGPU/trap-abis.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap-abis.ll
@@ -8,6 +8,7 @@
declare void @llvm.trap() #0
declare void @llvm.debugtrap() #1
+declare void @llvm.ubsantrap(i8) #2
define amdgpu_kernel void @trap(ptr addrspace(1) nocapture readonly %arg0) {
; NOHSA-TRAP-GFX900-LABEL: trap:
@@ -482,6 +483,134 @@ define amdgpu_kernel void @debugtrap(ptr addrspace(1) nocapture readonly %arg0)
ret void
}
+define void @ubsan_trap(ptr addrspace(1) nocapture readonly %arg0) {
+; CHECK-LABEL: ubsan_trap:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_trap 2
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+; NOHSA-TRAP-GFX900-LABEL: ubsan_trap:
+; NOHSA-TRAP-GFX900: ; %bb.0:
+; NOHSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; NOHSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 1
+; NOHSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
+; NOHSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-NEXT: s_cbranch_execnz .LBB4_2
+; NOHSA-TRAP-GFX900-NEXT: ; %bb.1:
+; NOHSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 2
+; NOHSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
+; NOHSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-NEXT: s_setpc_b64 s[30:31]
+; NOHSA-TRAP-GFX900-NEXT: .LBB4_2:
+; NOHSA-TRAP-GFX900-NEXT: s_endpgm
+;
+; HSA-TRAP-GFX803-LABEL: ubsan_trap:
+; HSA-TRAP-GFX803: ; %bb.0:
+; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX803-NEXT: flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v2, 2
+; HSA-TRAP-GFX803-NEXT: s_mov_b64 s[0:1], s[6:7]
+; HSA-TRAP-GFX803-NEXT: s_trap 2
+; HSA-TRAP-GFX803-NEXT: flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-NEXT: s_setpc_b64 s[30:31]
+;
+; HSA-TRAP-GFX900-LABEL: ubsan_trap:
+; HSA-TRAP-GFX900: ; %bb.0:
+; HSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; HSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
+; HSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 2
+; HSA-TRAP-GFX900-NEXT: s_trap 2
+; HSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
+; HSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; HSA-NOTRAP-GFX900-LABEL: ubsan_trap:
+; HSA-NOTRAP-GFX900: ; %bb.0:
+; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; HSA-NOTRAP-GFX900-NEXT: v_mov_b32_e32 v2, 1
+; HSA-NOTRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
+; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-NEXT: s_cbranch_execnz .LBB4_2
+; HSA-NOTRAP-GFX900-NEXT: ; %bb.1:
+; HSA-NOTRAP-GFX900-NEXT: v_mov_b32_e32 v2, 2
+; HSA-NOTRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
+; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-NEXT: s_setpc_b64 s[30:31]
+; HSA-NOTRAP-GFX900-NEXT: .LBB4_2:
+; HSA-NOTRAP-GFX900-NEXT: s_endpgm
+;
+; HSA-TRAP-GFX1100-LABEL: ubsan_trap:
+; HSA-TRAP-GFX1100: ; %bb.0:
+; HSA-TRAP-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; HSA-TRAP-GFX1100-NEXT: v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX1100-NEXT: global_store_b32 v[0:1], v2, off dlc
+; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
+; HSA-TRAP-GFX1100-NEXT: s_cbranch_execnz .LBB4_2
+; HSA-TRAP-GFX1100-NEXT: ; %bb.1:
+; HSA-TRAP-GFX1100-NEXT: v_mov_b32_e32 v2, 2
+; HSA-TRAP-GFX1100-NEXT: global_store_b32 v[0:1], v2, off dlc
+; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
+; HSA-TRAP-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; HSA-TRAP-GFX1100-NEXT: .LBB4_2:
+; HSA-TRAP-GFX1100-NEXT: s_trap 2
+; HSA-TRAP-GFX1100-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)
+; HSA-TRAP-GFX1100-NEXT: s_mov_b32 ttmp2, m0
+; HSA-TRAP-GFX1100-NEXT: s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX1100-NEXT: s_and_b32 s0, s0, 0x3ff
+; HSA-TRAP-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; HSA-TRAP-GFX1100-NEXT: s_bitset1_b32 s0, 10
+; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, s0
+; HSA-TRAP-GFX1100-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT)
+; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, ttmp2
+; HSA-TRAP-GFX1100-NEXT: .LBB4_3: ; =>This Inner Loop Header: Depth=1
+; HSA-TRAP-GFX1100-NEXT: s_sethalt 5
+; HSA-TRAP-GFX1100-NEXT: s_branch .LBB4_3
+;
+; HSA-TRAP-GFX1100-O0-LABEL: ubsan_trap:
+; HSA-TRAP-GFX1100-O0: ; %bb.0:
+; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, v1
+; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr0
+; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr0
+; HSA-TRAP-GFX1100-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
+; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v1, v2
+; HSA-TRAP-GFX1100-O0-NEXT: scratch_store_b64 off, v[0:1], s32 ; 8-byte Folded Spill
+; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr0_sgpr1
+; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX1100-O0-NEXT: global_store_b32 v[0:1], v2, off dlc
+; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt_vscnt null, 0x0
+; HSA-TRAP-GFX1100-O0-NEXT: s_cbranch_execnz .LBB4_2
+; HSA-TRAP-GFX1100-O0-NEXT: ; %bb.1:
+; HSA-TRAP-GFX1100-O0-NEXT: scratch_load_b64 v[0:1], off, s32 ; 8-byte Folded Reload
+; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, 2
+; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX1100-O0-NEXT: global_store_b32 v[0:1], v2, off dlc
+; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt_vscnt null, 0x0
+; HSA-TRAP-GFX1100-O0-NEXT: s_setpc_b64 s[30:31]
+; HSA-TRAP-GFX1100-O0-NEXT: .LBB4_2:
+; HSA-TRAP-GFX1100-O0-NEXT: s_trap 2
+; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)
+; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 ttmp2, m0
+; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX1100-O0-NEXT: s_and_b32 s0, s0, 0x3ff
+; HSA-TRAP-GFX1100-O0-NEXT: s_or_b32 s0, s0, 0x400
+; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, s0
+; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT)
+; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, ttmp2
+; HSA-TRAP-GFX1100-O0-NEXT: .LBB4_3: ; =>This Inner Loop Header: Depth=1
+; HSA-TRAP-GFX1100-O0-NEXT: s_sethalt 5
+; HSA-TRAP-GFX1100-O0-NEXT: s_branch .LBB4_3
+ store volatile i32 1, ptr addrspace(1) %arg0
+ call void @llvm.ubsantrap(i8 0)
+ store volatile i32 2, ptr addrspace(1) %arg0
+ ret void
+}
+
attributes #0 = { nounwind noreturn }
attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll
index 9bab3e6fcf8c4..c1b77abed9164 100644
--- a/llvm/test/CodeGen/AMDGPU/trap.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --function ubsantrap --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
@@ -28,6 +29,7 @@
declare void @llvm.trap() #0
declare void @llvm.debugtrap() #1
+declare void @llvm.ubsantrap(i8) #2
; MESA-TRAP: .section .AMDGPU.config
; MESA-TRAP: .long 47180
@@ -83,6 +85,13 @@ define amdgpu_kernel void @hsa_debugtrap(ptr addrspace(1) nocapture readonly %ar
ret void
}
+define amdgpu_kernel void @ubsantrap(ptr addrspace(1) nocapture readonly %arg0) {
+ store volatile i32 1, ptr addrspace(1) %arg0
+ call void @llvm.ubsantrap(i8 0)
+ store volatile i32 2, ptr addrspace(1) %arg0
+ ret void
+}
+
; For non-HSA path
; GCN-LABEL: {{^}}trap:
; TRAP-BIT: enable_trap_handler = 1
@@ -147,3 +156,13 @@ attributes #1 = { nounwind }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GCN: {{.*}}
+; GCN-WARNING: {{.*}}
+; HSA-TRAP: {{.*}}
+; MESA-TRAP: {{.*}}
+; NO-HSA-TRAP: {{.*}}
+; NO-MESA-TRAP: {{.*}}
+; NO-TRAP-BIT: {{.*}}
+; NOMESA-TRAP: {{.*}}
+; TRAP-BIT: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/ubsan_trap.ll b/llvm/test/CodeGen/AMDGPU/ubsan_trap.ll
deleted file mode 100644
index 9f961031a1ddb..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/ubsan_trap.ll
+++ /dev/null
@@ -1,7 +0,0 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel < %s
-; LLVM ERROR: cannot select: G_UBSANTRAP 0 (in function: ubsan_trap)
-
-define void @ubsan_trap() {
- call void @llvm.ubsantrap(i8 0)
- ret void
-}
\ No newline at end of file
>From 626119acacb2974a70740f3f677d86dea7654429 Mon Sep 17 00:00:00 2001
From: Aman Sharma <210100011 at iitb.ac.in>
Date: Tue, 13 May 2025 12:04:18 +0530
Subject: [PATCH 3/6] Updated trap.ll and merged debugtrap and ubsantrap
legalizers
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 33 ++++-----------
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 7 +---
llvm/test/CodeGen/AMDGPU/trap.ll | 42 +++++++------------
3 files changed, 25 insertions(+), 57 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index e6ebbe97c51ca..6cb300449fa60 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2221,9 +2221,9 @@ bool AMDGPULegalizerInfo::legalizeCustom(
case TargetOpcode::G_TRAP:
return legalizeTrap(MI, MRI, B);
case TargetOpcode::G_DEBUGTRAP:
- return legalizeDebugTrap(MI, MRI, B);
+ return legalizeDebugUbsanTrap(MI, MRI, B, TargetOpcode::G_DEBUGTRAP);
case TargetOpcode::G_UBSANTRAP:
- return legalizeUbsanTrap(MI, MRI, B);
+ return legalizeDebugUbsanTrap(MI, MRI, B, TargetOpcode::G_UBSANTRAP);
default:
return false;
}
@@ -7025,42 +7025,23 @@ bool AMDGPULegalizerInfo::legalizeTrapHsa(MachineInstr &MI,
return true;
}
-bool AMDGPULegalizerInfo::legalizeDebugTrap(MachineInstr &MI,
+bool AMDGPULegalizerInfo::legalizeDebugUbsanTrap(MachineInstr &MI,
MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const {
+ MachineIRBuilder &B, unsigned int Opcode) const {
// Is non-HSA path or trap-handler disabled? Then, report a warning
// accordingly
if (!ST.isTrapHandlerEnabled() ||
ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
DiagnosticInfoUnsupported NoTrap(B.getMF().getFunction(),
- "debugtrap handler not supported",
+ "debugtrap/ubsantrap handler not supported",
MI.getDebugLoc(), DS_Warning);
LLVMContext &Ctx = B.getMF().getFunction().getContext();
Ctx.diagnose(NoTrap);
- } else {
+ } else if (Opcode == TargetOpcode::G_DEBUGTRAP){
// Insert debug-trap instruction
B.buildInstr(AMDGPU::S_TRAP)
.addImm(static_cast<unsigned>(GCNSubtarget::TrapID::LLVMAMDHSADebugTrap));
- }
-
- MI.eraseFromParent();
- return true;
-}
-
-bool AMDGPULegalizerInfo::legalizeUbsanTrap(MachineInstr &MI,
- MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const {
- // Is non-HSA path or trap-handler disabled? Then, report a warning
- // accordingly
- if (!ST.isTrapHandlerEnabled() ||
- ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
- DiagnosticInfoUnsupported NoTrap(B.getMF().getFunction(),
- "ubsantrap handler not supported",
- MI.getDebugLoc(), DS_Warning);
- LLVMContext &Ctx = B.getContext();
- Ctx.diagnose(NoTrap);
- } else {
- // Insert trap instruction
+ } else if (Opcode == TargetOpcode::G_UBSANTRAP){
B.buildInstr(AMDGPU::S_TRAP)
.addImm(static_cast<unsigned>(GCNSubtarget::TrapID::LLVMAMDHSATrap));
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 076a66bb6012f..dd18ae33715e6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -241,11 +241,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
MachineIRBuilder &B) const;
bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
- bool legalizeDebugTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const;
-
- bool legalizeUbsanTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &B) const;
+ bool legalizeDebugUbsanTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
+ MachineIRBuilder &B, unsigned int Opcode) const;
bool legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const override;
diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll
index c1b77abed9164..8a7b61f392cc3 100644
--- a/llvm/test/CodeGen/AMDGPU/trap.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --function ubsantrap --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
@@ -6,25 +5,26 @@
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-1 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-2 %s
; enable trap handler feature
; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-1 -check-prefix=TRAP-BIT %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-2 -check-prefix=TRAP-BIT %s
; disable trap handler feature
; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-1 -check-prefix=NO-TRAP-BIT %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-2 -check-prefix=NO-TRAP-BIT %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-1 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-2 %s
-; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap handler not supported
+; GCN-WARNING-1: warning: <unknown>:0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap handler not supported
+; GCN-WARNING-2: warning: <unknown>:0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap/ubsantrap handler not supported
declare void @llvm.trap() #0
@@ -85,12 +85,12 @@ define amdgpu_kernel void @hsa_debugtrap(ptr addrspace(1) nocapture readonly %ar
ret void
}
-define amdgpu_kernel void @ubsantrap(ptr addrspace(1) nocapture readonly %arg0) {
- store volatile i32 1, ptr addrspace(1) %arg0
- call void @llvm.ubsantrap(i8 0)
- store volatile i32 2, ptr addrspace(1) %arg0
- ret void
-}
+;define amdgpu_kernel void @ubsantrap(ptr addrspace(1) nocapture readonly %arg0) {
+; store volatile i32 1, ptr addrspace(1) %arg0
+; call void @llvm.ubsantrap(i8 0)
+; store volatile i32 2, ptr addrspace(1) %arg0
+; ret void
+;}
; For non-HSA path
; GCN-LABEL: {{^}}trap:
@@ -156,13 +156,3 @@ attributes #1 = { nounwind }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GCN: {{.*}}
-; GCN-WARNING: {{.*}}
-; HSA-TRAP: {{.*}}
-; MESA-TRAP: {{.*}}
-; NO-HSA-TRAP: {{.*}}
-; NO-MESA-TRAP: {{.*}}
-; NO-TRAP-BIT: {{.*}}
-; NOMESA-TRAP: {{.*}}
-; TRAP-BIT: {{.*}}
>From 3445c015cebf4e6ba7fc8ce4ad7529be06fa71e7 Mon Sep 17 00:00:00 2001
From: Aman Sharma <210100011 at iitb.ac.in>
Date: Wed, 14 May 2025 12:48:15 +0530
Subject: [PATCH 4/6] Fixed GCN-WARNING mismatch
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +-
llvm/test/CodeGen/AMDGPU/trap.ll | 31 +++++++++++------------
2 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 21f8c7cfeec1f..922cf774dda9e 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -7284,7 +7284,7 @@ SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
if (!Subtarget->isTrapHandlerEnabled() ||
Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
- "debugtrap handler not supported",
+ "debugtrap/ubsantrap handler not supported",
Op.getDebugLoc(), DS_Warning);
LLVMContext &Ctx = MF.getFunction().getContext();
Ctx.diagnose(NoTrap);
diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll
index 8a7b61f392cc3..adbe2326b4e0f 100644
--- a/llvm/test/CodeGen/AMDGPU/trap.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap.ll
@@ -5,26 +5,25 @@
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-1 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-2 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
; enable trap handler feature
; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-1 -check-prefix=TRAP-BIT %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-2 -check-prefix=TRAP-BIT %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s
; disable trap handler feature
; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-1 -check-prefix=NO-TRAP-BIT %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-2 -check-prefix=NO-TRAP-BIT %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-1 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING-2 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
-; GCN-WARNING-1: warning: <unknown>:0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap handler not supported
-; GCN-WARNING-2: warning: <unknown>:0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap/ubsantrap handler not supported
+; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap/ubsantrap handler not supported
declare void @llvm.trap() #0
@@ -85,12 +84,12 @@ define amdgpu_kernel void @hsa_debugtrap(ptr addrspace(1) nocapture readonly %ar
ret void
}
-;define amdgpu_kernel void @ubsantrap(ptr addrspace(1) nocapture readonly %arg0) {
-; store volatile i32 1, ptr addrspace(1) %arg0
-; call void @llvm.ubsantrap(i8 0)
-; store volatile i32 2, ptr addrspace(1) %arg0
-; ret void
-;}
+define amdgpu_kernel void @ubsantrap(ptr addrspace(1) nocapture readonly %arg0) {
+ store volatile i32 1, ptr addrspace(1) %arg0
+ call void @llvm.ubsantrap(i8 0)
+ store volatile i32 2, ptr addrspace(1) %arg0
+ ret void
+}
; For non-HSA path
; GCN-LABEL: {{^}}trap:
>From 7835b116df5a03207e65e57a69def0f5517266ab Mon Sep 17 00:00:00 2001
From: Aman Sharma <210100011 at iitb.ac.in>
Date: Wed, 14 May 2025 12:50:34 +0530
Subject: [PATCH 5/6] Fixed code style
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 922cf774dda9e..07da7c121befc 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -7283,9 +7283,9 @@ SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
if (!Subtarget->isTrapHandlerEnabled() ||
Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
- DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
- "debugtrap/ubsantrap handler not supported",
- Op.getDebugLoc(), DS_Warning);
+ DiagnosticInfoUnsupported NoTrap(
+ MF.getFunction(), "debugtrap/ubsantrap handler not supported",
+ Op.getDebugLoc(), DS_Warning);
LLVMContext &Ctx = MF.getFunction().getContext();
Ctx.diagnose(NoTrap);
return Chain;
>From 8322f92d0150c96343c771dffba9e98ad01ed574 Mon Sep 17 00:00:00 2001
From: Aman Sharma <210100011 at iitb.ac.in>
Date: Wed, 14 May 2025 12:59:51 +0530
Subject: [PATCH 6/6] Updated test
---
llvm/test/CodeGen/AMDGPU/trap.ll | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll
index adbe2326b4e0f..259d0646c4caa 100644
--- a/llvm/test/CodeGen/AMDGPU/trap.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap.ll
@@ -84,6 +84,25 @@ define amdgpu_kernel void @hsa_debugtrap(ptr addrspace(1) nocapture readonly %ar
ret void
}
+; MESA-TRAP: .section .AMDGPU.config
+; MESA-TRAP: .long 47180
+; MESA-TRAP-NEXT: .long 5080
+
+; NOMESA-TRAP: .section .AMDGPU.config
+; NOMESA-TRAP: .long 47180
+; NOMESA-TRAP-NEXT: .long 5016
+
+; GCN-LABEL: {{^}}ubsantrap:
+; HSA-TRAP: s_trap 2
+; HSA-TRAP: flat_store_dword v[0:1], v3
+; HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
+
+; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction
+; NO-HSA-TRAP: s_endpgm
+
+; TRAP-BIT: enable_trap_handler = 1
+; NO-TRAP-BIT: enable_trap_handler = 0
+; NO-MESA-TRAP: s_endpgm
define amdgpu_kernel void @ubsantrap(ptr addrspace(1) nocapture readonly %arg0) {
store volatile i32 1, ptr addrspace(1) %arg0
call void @llvm.ubsantrap(i8 0)
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