[llvm] [RISCV][VLOPT] Skip EMUL if it is unknown before entering EMULAndEEWAreEqual (PR #139670)

Piyou Chen via llvm-commits llvm-commits at lists.llvm.org
Tue May 13 23:05:25 PDT 2025


https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/139670

>From 54ae24e655d80337fcc6257142adc7ab9ac77c71 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Mon, 12 May 2025 23:18:40 -0700
Subject: [PATCH 1/4] [RISCV][VLOPT] skip EMUL is unknown before enter
 EMULAndEEWAreEqual

Fix https://github.com/llvm/llvm-project/issues/139288
---
 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp    |  5 +++++
 .../CodeGen/RISCV/rvv/139288-VLOPT-crash.ll   | 22 +++++++++++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/139288-VLOPT-crash.ll

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 9ed2ba274bc53..88876201ae21b 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1383,6 +1383,11 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
     // If the operand is used as a scalar operand, then the EEW must be
     // compatible. Otherwise, the EMUL *and* EEW must be compatible.
     bool IsVectorOpUsedAsScalarOp = isVectorOpUsedAsScalarOp(UserOp);
+
+    if (!IsVectorOpUsedAsScalarOp &&
+        (!ConsumerInfo->EMUL || !ProducerInfo->EMUL))
+      return std::nullopt;
+
     if ((IsVectorOpUsedAsScalarOp &&
          !OperandInfo::EEWAreEqual(*ConsumerInfo, *ProducerInfo)) ||
         (!IsVectorOpUsedAsScalarOp &&
diff --git a/llvm/test/CodeGen/RISCV/rvv/139288-VLOPT-crash.ll b/llvm/test/CodeGen/RISCV/rvv/139288-VLOPT-crash.ll
new file mode 100644
index 0000000000000..1e2f0173505c3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/139288-VLOPT-crash.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
+
+define i32 @pps_is_equal(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1) #0 {
+; CHECK-LABEL: pps_is_equal:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e32, m8, ta, ma
+; CHECK-NEXT:    vmclr.m v8
+; CHECK-NEXT:    vmv.s.x v16, zero
+; CHECK-NEXT:    vmor.mm v0, v8, v8
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vredmax.vs v8, v8, v16, v0.t
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+entry:
+    %2 = tail call <vscale x 16 x i1> @llvm.vp.or.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %0, i32 1)
+    %3 = tail call i32 @llvm.vp.reduce.smax.nxv16i32(i32 0, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i1> %2, i32 1)
+    ret i32 %3
+}
+
+declare <vscale x 16 x i1> @llvm.vp.or.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i32) #1
+declare i32 @llvm.vp.reduce.smax.nxv16i32(i32, <vscale x 16 x i32>, <vscale x 16 x i1>, i32) #1

>From 866f37cf167b90947e4b385857111560b4fa1090 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 13 May 2025 22:55:45 -0700
Subject: [PATCH 2/4] !fixup change on EMULAndEEWAreEqual

---
 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 88876201ae21b..88a8b01f4a4e2 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -83,8 +83,7 @@ struct OperandInfo {
   OperandInfo() = delete;
 
   static bool EMULAndEEWAreEqual(const OperandInfo &A, const OperandInfo &B) {
-    return A.Log2EEW == B.Log2EEW && A.EMUL->first == B.EMUL->first &&
-           A.EMUL->second == B.EMUL->second;
+    return A.Log2EEW == B.Log2EEW && A.EMUL == B.EMUL;
   }
 
   static bool EEWAreEqual(const OperandInfo &A, const OperandInfo &B) {
@@ -1384,10 +1383,6 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
     // compatible. Otherwise, the EMUL *and* EEW must be compatible.
     bool IsVectorOpUsedAsScalarOp = isVectorOpUsedAsScalarOp(UserOp);
 
-    if (!IsVectorOpUsedAsScalarOp &&
-        (!ConsumerInfo->EMUL || !ProducerInfo->EMUL))
-      return std::nullopt;
-
     if ((IsVectorOpUsedAsScalarOp &&
          !OperandInfo::EEWAreEqual(*ConsumerInfo, *ProducerInfo)) ||
         (!IsVectorOpUsedAsScalarOp &&

>From ffaabce874ddfcb7597fc97322ee8c1c4a795504 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 13 May 2025 22:56:24 -0700
Subject: [PATCH 3/4] !fixup move the testcase

---
 .../CodeGen/RISCV/rvv/139288-VLOPT-crash.ll   | 22 ----------------
 llvm/test/CodeGen/RISCV/rvv/vl-opt.mir        | 25 +++++++++++++++++++
 2 files changed, 25 insertions(+), 22 deletions(-)
 delete mode 100644 llvm/test/CodeGen/RISCV/rvv/139288-VLOPT-crash.ll

diff --git a/llvm/test/CodeGen/RISCV/rvv/139288-VLOPT-crash.ll b/llvm/test/CodeGen/RISCV/rvv/139288-VLOPT-crash.ll
deleted file mode 100644
index 1e2f0173505c3..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/139288-VLOPT-crash.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
-
-define i32 @pps_is_equal(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1) #0 {
-; CHECK-LABEL: pps_is_equal:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 1, e32, m8, ta, ma
-; CHECK-NEXT:    vmclr.m v8
-; CHECK-NEXT:    vmv.s.x v16, zero
-; CHECK-NEXT:    vmor.mm v0, v8, v8
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vredmax.vs v8, v8, v16, v0.t
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    ret
-entry:
-    %2 = tail call <vscale x 16 x i1> @llvm.vp.or.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %0, i32 1)
-    %3 = tail call i32 @llvm.vp.reduce.smax.nxv16i32(i32 0, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i1> %2, i32 1)
-    ret i32 %3
-}
-
-declare <vscale x 16 x i1> @llvm.vp.or.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i32) #1
-declare i32 @llvm.vp.reduce.smax.nxv16i32(i32, <vscale x 16 x i32>, <vscale x 16 x i1>, i32) #1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index 6343afc6bac62..988335126e62e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -498,4 +498,29 @@ body: |
     %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
     PseudoBR %bb.1
 ...
+---
+name: EMUL_is_unknown
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    ; CHECK-LABEL: name: EMUL_is_unknown
+    ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 1, 0 /* e8 */
+    ; CHECK-NEXT: [[PseudoVMOR_MM_B4_:%[0-9]+]]:vmv0 = PseudoVMOR_MM_B4 [[PseudoVMCLR_M_B4_]], [[PseudoVMCLR_M_B4_]], 1, 0 /* e8 */
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+    ; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X $noreg, [[COPY]], 1, 5 /* e32 */
+    ; CHECK-NEXT: [[PseudoVMV_V_I_M8_:%[0-9]+]]:vrm8 = PseudoVMV_V_I_M8 $noreg, 0, 1, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: [[PseudoVREDMAX_VS_M8_E32_MASK:%[0-9]+]]:vrnov0 = PseudoVREDMAX_VS_M8_E32_MASK $noreg, killed [[PseudoVMV_V_I_M8_]], killed [[PseudoVMV_S_X]], [[PseudoVMOR_MM_B4_]], 1, 5 /* e32 */, 1 /* ta, mu */
+    ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S killed [[PseudoVREDMAX_VS_M8_E32_MASK]], 5 /* e32 */
+    ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %2:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+    %3:vmv0 = PseudoVMOR_MM_B4 %2, %2, 1, 0 /* e8 */
+    %4:gpr = COPY $x0
+    %5:vr = PseudoVMV_S_X $noreg, %4, 1, 5 /* e32 */
+    %6:vrm8 = PseudoVMV_V_I_M8 $noreg, 0, 1, 5 /* e32 */, 0 /* tu, mu */
+    %7:vrnov0 = PseudoVREDMAX_VS_M8_E32_MASK $noreg, killed %6, killed %5, %3, 1, 5 /* e32 */, 1 /* ta, mu */
+    %9:gpr = PseudoVMV_X_S killed %7, 5 /* e32 */
+    $x10 = COPY %9
+    PseudoRET implicit $x10
+...
 

>From e1a1954bc5463503260c48b57b4b9fbcaaaad6ed Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 13 May 2025 23:05:12 -0700
Subject: [PATCH 4/4] !fixup update format

---
 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 88a8b01f4a4e2..f7cbfa1546de6 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1382,7 +1382,6 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
     // If the operand is used as a scalar operand, then the EEW must be
     // compatible. Otherwise, the EMUL *and* EEW must be compatible.
     bool IsVectorOpUsedAsScalarOp = isVectorOpUsedAsScalarOp(UserOp);
-
     if ((IsVectorOpUsedAsScalarOp &&
          !OperandInfo::EEWAreEqual(*ConsumerInfo, *ProducerInfo)) ||
         (!IsVectorOpUsedAsScalarOp &&



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