[llvm] [RISCV] Lower i64 load/stores to ld/sd with Zilsd. (PR #139808)

[Craig Topper via llvm-commits]

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@@ -13714,6 +13739,28 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
     // sext_inreg we emit for ADD/SUB/MUL/SLLI.
     LoadSDNode *Ld = cast<LoadSDNode>(N);
 
+    if (N->getValueType(0) == MVT::i64) {
+      assert(Subtarget.hasStdExtZilsd() && !Subtarget.is64Bit() &&
+             "Unexpected custom legalisation");
+
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topperc wrote:

Line 13735

https://github.com/llvm/llvm-project/pull/139808