[llvm] [TableGen] Avoid assignmentInAssert warning (PR #139715)

[Qinkun Bao via llvm-commits]

qinkunbao wrote:

Hi,

This PR broke a few build bots.
https://lab.llvm.org/buildbot/#/builders/66/builds/13885/steps/8/logs/stdio

Before
```
assert(ExpectedID++ == ID && "combine rules are not ordered!");
```

The code compares ExpectedID with ID first and then adds +1 to  ExpectedID


Now
```
 ++ExpectedID;
 assert(ExpectedID == ID && "combine rules are not ordered!");
```

The code adds +1 to  ExpectedID and then compare it with ID. The change are not semantically equivalent.




https://github.com/llvm/llvm-project/pull/139715