[llvm] [Codegen][Backend] Remove redundant pseudo mov instruction (PR #139716)

[Rohit Aggarwal via llvm-commits]

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@@ -186,11 +186,13 @@ static bool isCandidate(const MachineInstr *MI, Register &DefedReg,
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     if (MO.isReg()) {
-      if (MO.isDef()) {
+      if (MO.isDef() && DefedReg == MCRegister::NoRegister) {
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rohitaggarwal007 wrote:

In some case instruction's MachineOperands MO.isDef() is getting true for more than one operand. Instruction having more than one define. So it just add a check that if the **DefedReg** is not assigned then try to find the value of register and assign it to **DefedReg**. Once it is assigned, do not reassign it. 

As per my understanding, in any instruction's MOs there is only def and all other are use().

Please correct me if my understanding is incorrect.

https://github.com/llvm/llvm-project/pull/139716