[llvm] 6c6413f - [TableGen] Fixup #139715

via llvm-commits llvm-commits at lists.llvm.org
Tue May 13 05:22:16 PDT 2025


Author: pvanhout
Date: 2025-05-13T14:22:07+02:00
New Revision: 6c6413f3f973862c7275e7baecdd4bb6bcf430c9

URL: https://github.com/llvm/llvm-project/commit/6c6413f3f973862c7275e7baecdd4bb6bcf430c9
DIFF: https://github.com/llvm/llvm-project/commit/6c6413f3f973862c7275e7baecdd4bb6bcf430c9.diff

LOG: [TableGen] Fixup #139715

The increment must be after the assert, not before, otherwise the assert fails everytime.

Added: 
    

Modified: 
    llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp

Removed: 
    


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diff  --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index d11812b651b7c..f09598286e548 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -2611,8 +2611,8 @@ void GICombinerEmitter::emitTestSimplePredicate(raw_ostream &OS) {
     // (GICXXPred_Invalid + 1).
     unsigned ExpectedID = 0;
     for (const auto &ID : keys(AllCombineRules)) {
-      ++ExpectedID;
       assert(ExpectedID == ID && "combine rules are not ordered!");
+      ++ExpectedID;
       OS << "  " << getIsEnabledPredicateEnumName(ID) << EnumeratorSeparator;
       EnumeratorSeparator = ",\n";
     }


        


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