[llvm] [TableGen] Avoid assignmentInAssert warning (PR #139715)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `clang-armv7-lnt` running on `linaro-clang-armv7-lnt` while building `llvm` at step 6 "build stage 1".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/77/builds/12301

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 6 (build stage 1) failure: 'ninja' (failure)
...
[63/1542] Building BPFGenInstrInfo.inc...
[64/1508] Building MSP430GenSDNodeInfo.inc...
[65/1507] Building MipsGenRegisterBank.inc...
[66/1507] Building HexagonGenDisassemblerTables.inc...
[67/1507] Building R600GenDFAPacketizer.inc...
[68/1507] Building MipsGenRegisterInfo.inc...
[69/1507] Building LoongArchGenAsmMatcher.inc...
[70/1507] Building MipsGenMCPseudoLowering.inc...
[71/1507] Building LoongArchGenDisassemblerTables.inc...
[72/1507] Building AArch64GenPostLegalizeGICombiner.inc...
FAILED: lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc /home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc 
cd /home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/lib/Target/AArch64 && /home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/bin/llvm-tblgen -gen-global-isel-combiner -combiners="AArch64PostLegalizerCombiner" -I /home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm/lib/Target/AArch64 -I/home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/include -I/home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm/include -I /home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm/lib/Target /home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm/lib/Target/AArch64/AArch64.td --write-if-changed -o AArch64GenPostLegalizeGICombiner.inc -d AArch64GenPostLegalizeGICombiner.inc.d && /usr/local/bin/cmake -E cmake_transform_depfile Ninja gccdepfile /home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm /home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm/lib/Target/AArch64 /home/tcwg-buildbot/worker/clang-armv7-lnt/stage1 /home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/lib/Target/AArch64 /home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc.d /home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/CMakeFiles/d/980955217980d8e9409156de10a1cc7feaca2cf7761e6ed28fadf93408aa43bb.d
llvm-tblgen: ../llvm/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp:2615: virtual void (anonymous namespace)::GICombinerEmitter::emitTestSimplePredicate(raw_ostream &): Assertion `ExpectedID == ID && "combine rules are not ordered!"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/bin/llvm-tblgen -gen-global-isel-combiner -combiners=AArch64PostLegalizerCombiner -I /home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm/lib/Target/AArch64 -I/home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/include -I/home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm/include -I /home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm/lib/Target /home/tcwg-buildbot/worker/clang-armv7-lnt/llvm/llvm/lib/Target/AArch64/AArch64.td --write-if-changed -o AArch64GenPostLegalizeGICombiner.inc -d AArch64GenPostLegalizeGICombiner.inc.d
#0 0x0cf4c908 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/bin/llvm-tblgen+0x35c908)
#1 0x0cf4a300 llvm::sys::RunSignalHandlers() (/home/tcwg-buildbot/worker/clang-armv7-lnt/stage1/bin/llvm-tblgen+0x35a300)
#2 0x0cf4d1c0 SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
#3 0xec2dd6f0 __default_rt_sa_restorer ./signal/../sysdeps/unix/sysv/linux/arm/sigrestorer.S:80:0
#4 0xec2cdb06 ./csu/../sysdeps/unix/sysv/linux/arm/libc-do-syscall.S:47:0
#5 0xec30d292 __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
#6 0xec2dc840 gsignal ./signal/../sysdeps/posix/raise.c:27:6
Aborted
[73/1507] Building PPCGenRegisterBank.inc...
[74/1507] Building PPCGenMCCodeEmitter.inc...
[75/1507] Building MipsGenPostLegalizeGICombiner.inc...
[76/1507] Building ARMGenRegisterInfo.inc...
[77/1507] Building MipsGenMCCodeEmitter.inc...
[78/1507] Building MSP430GenDAGISel.inc...
[79/1507] Building ARMGenRegisterBank.inc...
[80/1507] Building AArch64GenMCCodeEmitter.inc...
[81/1507] Building AVRGenInstrInfo.inc...
[82/1483] Building MSP430GenAsmMatcher.inc...
[83/1483] Building NVPTXGenSubtargetInfo.inc...
[84/1483] Building MSP430GenAsmWriter.inc...
[85/1483] Building LoongArchGenMCCodeEmitter.inc...
[86/1483] Building MipsGenAsmWriter.inc...
[87/1483] Building LanaiGenInstrInfo.inc...
[88/1483] Building ARMGenFastISel.inc...
[89/1483] Building ARMGenAsmWriter.inc...
[90/1483] Building AArch64GenDisassemblerTables.inc...
[91/1483] Building NVPTXGenRegisterInfo.inc...
[92/1483] Building PPCGenCallingConv.inc...
[93/1483] Building MipsGenDisassemblerTables.inc...
[94/1483] Building MSP430GenMCCodeEmitter.inc...
[95/1483] Building PPCGenAsmWriter.inc...
[96/1483] Building MipsGenFastISel.inc...
[97/1483] Building LanaiGenSubtargetInfo.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/139715