[llvm] 8be514c - [TableGen] Avoid assignmentInAssert warning (#139715)

[via llvm-commits]

Author: Pierre van Houtryve
Date: 2025-05-13T14:08:33+02:00
New Revision: 8be514cc96345feb35d8d8a372ee771c6d69a73f

URL: https://github.com/llvm/llvm-project/commit/8be514cc96345feb35d8d8a372ee771c6d69a73f
DIFF: https://github.com/llvm/llvm-project/commit/8be514cc96345feb35d8d8a372ee771c6d69a73f.diff

LOG: [TableGen] Avoid assignmentInAssert warning (#139715)

ExpectedID should be optimized out anyway if built without assertions
because nothing reads its value.

Fixes #90327

Added: 
    

Modified: 
    llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp

Removed: 
    


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diff  --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index 36c0cf529e32f..d11812b651b7c 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -2610,9 +2610,9 @@ void GICombinerEmitter::emitTestSimplePredicate(raw_ostream &OS) {
     // That way we can just get the RuleID from the enum by subtracting
     // (GICXXPred_Invalid + 1).
     unsigned ExpectedID = 0;
-    (void)ExpectedID;
     for (const auto &ID : keys(AllCombineRules)) {
-      assert(ExpectedID++ == ID && "combine rules are not ordered!");
+      ++ExpectedID;
+      assert(ExpectedID == ID && "combine rules are not ordered!");
       OS << "  " << getIsEnabledPredicateEnumName(ID) << EnumeratorSeparator;
       EnumeratorSeparator = ",\n";
     }