[llvm] [SelectionDAG] Add an ISD node for for get.active.lane.mask (PR #139084)

[Paul Walker via llvm-commits]

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@@ -29515,6 +29509,27 @@ AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
   return DAG.getNode(ISD::ADD, DL, ResultVT, Acc, Extended);
 }
 
+SDValue
+AArch64TargetLowering::LowerGET_ACTIVE_LANE_MASK(SDValue Op,
+                                                 SelectionDAG &DAG) const {
+  EVT VT = Op.getValueType();
+  assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
+
+  // We can use the SVE whilelo instruction to lower this intrinsic by
+  // creating the appropriate sequence of scalable vector operations and
+  // then extracting a fixed-width subvector from the scalable vector.
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paulwalker-arm wrote:

This doesn't strictly match the code.  Perhaps something simpler like "No dedicated fixed length instructions but we can use SVE when available." ?

On which note, I think it's worth adding an assert for `Subtarget->isSVEorStreamingSVEAvailable()`.

https://github.com/llvm/llvm-project/pull/139084