[llvm] [AggressiveInstCombine] Check GEP nusw, not inbounds (PR #139708)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Tue May 13 04:10:05 PDT 2025
https://github.com/artagnon created https://github.com/llvm/llvm-project/pull/139708
None
>From a1a4836689bc6e04adb2071a3e197f0f846603ee Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Tue, 13 May 2025 11:50:36 +0100
Subject: [PATCH 1/2] [AggressiveInstCombine] Pre-commit nusw tests
---
.../lower-table-based-cttz-basics.ll | 25 +++++++++++++++++++
.../AggressiveInstCombine/patterned-load.ll | 14 +++++++++++
2 files changed, 39 insertions(+)
diff --git a/llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll b/llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll
index 9a6c59b91aca5..01c1d561dad66 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll
@@ -113,6 +113,31 @@ entry:
ret i32 %conv
}
+define i32 @ctz1_nusw(i32 %x) {
+; CHECK-LABEL: @ctz1_nusw(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[SUB]], [[X]]
+; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AND]], 125613361
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[MUL]], 27
+; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[SHR]] to i64
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr nusw [32 x i8], ptr @ctz7.table, i64 0, i64 [[IDXPROM]]
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
+; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP3]] to i32
+; CHECK-NEXT: ret i32 [[CONV]]
+;
+entry:
+ %sub = sub i32 0, %x
+ %and = and i32 %sub, %x
+ %mul = mul i32 %and, 125613361
+ %shr = lshr i32 %mul, 27
+ %idxprom = zext i32 %shr to i64
+ %arrayidx = getelementptr nusw [32 x i8], ptr @ctz7.table, i64 0, i64 %idxprom
+ %0 = load i8, ptr %arrayidx, align 1
+ %conv = zext i8 %0 to i32
+ ret i32 %conv
+}
+
@ctz2.table = internal unnamed_addr constant [64 x i16] [i16 32, i16 0, i16 1, i16 12, i16 2, i16 6, i16 0, i16 13, i16 3, i16 0, i16 7, i16 0, i16 0, i16 0, i16 0, i16 14, i16 10, i16 4, i16 0, i16 0, i16 8, i16 0, i16 0, i16 25, i16 0, i16 0, i16 0, i16 0, i16 0, i16 21, i16 27, i16 15, i16 31, i16 11, i16 5, i16 0, i16 0, i16 0, i16 0, i16 0, i16 9, i16 0, i16 0, i16 24, i16 0, i16 0, i16 20, i16 26, i16 30, i16 0, i16 0, i16 0, i16 0, i16 23, i16 0, i16 19, i16 29, i16 0, i16 22, i16 18, i16 28, i16 17, i16 16, i16 0], align 2
define i32 @ctz2(i32 %x) {
diff --git a/llvm/test/Transforms/AggressiveInstCombine/patterned-load.ll b/llvm/test/Transforms/AggressiveInstCombine/patterned-load.ll
index e43dad2ca0893..009546dd383dd 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/patterned-load.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/patterned-load.ll
@@ -140,6 +140,20 @@ define i32 @gep_load_i32_align2_const_offset_wrap(i64 %idx){
ret i32 %3
}
+define i32 @gep_load_i32_align2_const_offset_nusw(i64 %idx){
+; CHECK-LABEL: @gep_load_i32_align2_const_offset_nusw(
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr nusw i16, ptr @constarray2, i64 -2
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr nusw [3 x i16], ptr [[TMP1]], i64 [[IDX:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 2
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = getelementptr nusw i16, ptr @constarray2, i64 -2
+ %2 = getelementptr nusw [3 x i16], ptr %1, i64 %idx
+ %3 = load i32, ptr %2, align 2
+ ret i32 %3
+}
+
+
define i32 @inbounds_gep_i32_load_i32_const_ptr_array(i64 %idx){
; CHECK-LABEL: @inbounds_gep_i32_load_i32_const_ptr_array(
; CHECK-NEXT: ret i32 42
>From 802f790f142ea5bb22720a90f93101171f148bec Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Tue, 13 May 2025 11:59:16 +0100
Subject: [PATCH 2/2] [AggressiveInstCombine] Check GEP nusw, not inbounds
---
.../AggressiveInstCombine/AggressiveInstCombine.cpp | 4 ++--
.../lower-table-based-cttz-basics.ll | 11 ++++-------
.../AggressiveInstCombine/patterned-load.ll | 10 +++++-----
3 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
index af994022a8ec1..3eca3943a8224 100644
--- a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+++ b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
@@ -530,7 +530,7 @@ static bool tryToRecognizeTableBasedCttz(Instruction &I) {
return false;
GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(LI->getPointerOperand());
- if (!GEP || !GEP->isInBounds() || GEP->getNumIndices() != 2)
+ if (!GEP || !GEP->hasNoUnsignedSignedWrap() || GEP->getNumIndices() != 2)
return false;
if (!GEP->getSourceElementType()->isArrayTy())
@@ -843,7 +843,7 @@ getStrideAndModOffsetOfGEP(Value *PtrOp, const DataLayout &DL) {
for (auto [V, Scale] : VarOffsets) {
// Only keep a power of two factor for non-inbounds
- if (!GEP->isInBounds())
+ if (!GEP->hasNoUnsignedSignedWrap())
Scale = APInt::getOneBitSet(Scale.getBitWidth(), Scale.countr_zero());
if (!Stride)
diff --git a/llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll b/llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll
index 01c1d561dad66..4d571999df372 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll
@@ -116,13 +116,10 @@ entry:
define i32 @ctz1_nusw(i32 %x) {
; CHECK-LABEL: @ctz1_nusw(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[SUB]], [[X]]
-; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AND]], 125613361
-; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[MUL]], 27
-; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[SHR]] to i64
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr nusw [32 x i8], ptr @ctz7.table, i64 0, i64 [[IDXPROM]]
-; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 0, i32 [[TMP0]]
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP3]] to i32
; CHECK-NEXT: ret i32 [[CONV]]
;
diff --git a/llvm/test/Transforms/AggressiveInstCombine/patterned-load.ll b/llvm/test/Transforms/AggressiveInstCombine/patterned-load.ll
index 009546dd383dd..55e75230148c5 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/patterned-load.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/patterned-load.ll
@@ -141,11 +141,11 @@ define i32 @gep_load_i32_align2_const_offset_wrap(i64 %idx){
}
define i32 @gep_load_i32_align2_const_offset_nusw(i64 %idx){
-; CHECK-LABEL: @gep_load_i32_align2_const_offset_nusw(
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr nusw i16, ptr @constarray2, i64 -2
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr nusw [3 x i16], ptr [[TMP1]], i64 [[IDX:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 2
-; CHECK-NEXT: ret i32 [[TMP3]]
+; LE-LABEL: @gep_load_i32_align2_const_offset_nusw(
+; LE-NEXT: ret i32 65537
+;
+; BE-LABEL: @gep_load_i32_align2_const_offset_nusw(
+; BE-NEXT: ret i32 16777472
;
%1 = getelementptr nusw i16, ptr @constarray2, i64 -2
%2 = getelementptr nusw [3 x i16], ptr %1, i64 %idx
More information about the llvm-commits
mailing list