[llvm] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX pre-regbankselect (PR #131309)

[Pierre van Houtryve via llvm-commits]

Pierre-vh wrote:

> We don't have 16-bit BFE instructions, so I don't understand why you would do this

The BFX formation combines check legality, but if U/SBFX with s16 is illegal it won't do it
However if we make it legal, and widen in RBSelect instead, it works and we can generate a smaller instruction sequence, see `v_lshr_i8_7` test for example

I feel like having BFX work on many types is useful, even if codegen ends up generating it with ext/truncs. Matching all the possible shift/and combinations for bitfield extracts can get repetitive

https://github.com/llvm/llvm-project/pull/131309