[llvm] [AArch64][SME] Disable hazard padding when there is only PPRs and GPRs (PR #137817)

[Gaëtan Bossu via llvm-commits]

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@@ -3533,6 +3533,12 @@ static std::optional<int> getLdStFrameID(const MachineInstr &MI,
   return getMMOFrameID(*MI.memoperands_begin(), MFI);
 }
 
+/// Returns true if PPRs are spilled as ZPRs.
+static bool arePPRsSpilledAsZPR(const MachineFunction &MF) {
+  return MF.getSubtarget().getRegisterInfo()->getSpillSize(
+             AArch64::PPRRegClass) == 16;
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gbossu wrote:

Curious: In which case aren't predicates spilled using Z registers?

https://github.com/llvm/llvm-project/pull/137817