[llvm] Added support for extension Arbitrary_precision_floating_point (PR #139680)
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 13 00:27:06 PDT 2025
https://github.com/sumesh-s-mcw created https://github.com/llvm/llvm-project/pull/139680
Added support for the Extension Arbitrary_precision_floating_point
Added test files
>From 75680f5263394c7b288973be78166a65fde77cc2 Mon Sep 17 00:00:00 2001
From: sumesh-s-mcw <sumesh.suresh at multicorewareinc.com>
Date: Mon, 5 May 2025 14:16:55 +0530
Subject: [PATCH] Added support for extension
Arbitrary_precision_floating_point
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 50 +
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 44 +
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 6 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 103 ++
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 52 +-
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 2 +
...lity-arbitrary-precision-floating-point.ll | 1237 +++++++++++++++++
7 files changed, 1491 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/capability-arbitrary-precision-floating-point.ll
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index c516be0297e66..f84351b9b811e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2731,6 +2731,54 @@ static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call,
return true;
}
+static bool generateAFPInst(const SPIRV::IncomingCall *Call,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ const auto *Builtin = Call->Builtin;
+ auto *MRI = MIRBuilder.getMRI();
+ unsigned Opcode =
+ SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
+ const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType);
+ bool IsVoid = RetTy->isVoidTy();
+ auto MIB = MIRBuilder.buildInstr(Opcode);
+ // Handle return value or destination for void return.
+ Register DestReg;
+ if (IsVoid) {
+ LLT PtrTy = MRI->getType(Call->Arguments[0]);
+ DestReg = MRI->createGenericVirtualRegister(PtrTy);
+ MRI->setRegClass(DestReg, &SPIRV::pIDRegClass);
+
+ SPIRVType *PointeeTy =
+ GR->getPointeeType(GR->getSPIRVTypeForVReg(Call->Arguments[0]));
+ MIB.addDef(DestReg);
+ MIB.addUse(GR->getSPIRVTypeID(PointeeTy));
+ } else {
+ MIB.addDef(Call->ReturnRegister);
+ MIB.addUse(GR->getSPIRVTypeID(Call->ReturnType));
+ }
+ // Add arguments to instruction
+ for (unsigned i = IsVoid ? 1 : 0; i < Call->Arguments.size(); ++i) {
+ Register Arg = Call->Arguments[i];
+ MachineInstr *DefMI = MRI->getUniqueVRegDef(Arg);
+
+ if (DefMI->getOpcode() == TargetOpcode::G_CONSTANT &&
+ DefMI->getOperand(1).isCImm()) {
+ MIB.addImm(getConstFromIntrinsic(Arg, MRI));
+ } else {
+ MIB.addUse(Arg);
+ }
+ }
+ // Store result if return is void
+ if (IsVoid) {
+ LLT PtrTy = MRI->getType(Call->Arguments[0]);
+ MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOStore,
+ PtrTy.getSizeInBytes(), Align(4));
+ MIRBuilder.buildStore(DestReg, Call->Arguments[0], *MMO);
+ }
+ return true;
+}
+
namespace SPIRV {
// Try to find a builtin function attributes by a demangled function name and
// return a tuple <builtin group, op code, ext instruction number>, or a special
@@ -2902,6 +2950,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
case SPIRV::TernaryBitwiseINTEL:
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
+ case SPIRV::ArbitraryFloatingPoint:
+ return generateAFPInst(Call.get(), MIRBuilder, GR);
}
return false;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index 59cd38126cc01..2761115b31bea 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -68,6 +68,7 @@ def ICarryBorrow : BuiltinGroup;
def ExtendedBitOps : BuiltinGroup;
def BindlessINTEL : BuiltinGroup;
def TernaryBitwiseINTEL : BuiltinGroup;
+def ArbitraryFloatingPoint: BuiltinGroup;
//===----------------------------------------------------------------------===//
// Class defining a demangled builtin record. The information in the record
@@ -710,6 +711,49 @@ defm : DemangledNativeBuiltin<"__spirv_CooperativeMatrixStoreCheckedINTEL", Open
defm : DemangledNativeBuiltin<"__spirv_CooperativeMatrixConstructCheckedINTEL", OpenCL_std, CoopMatr, 5, 5, OpCooperativeMatrixConstructCheckedINTEL>;
defm : DemangledNativeBuiltin<"__spirv_CooperativeMatrixGetElementCoordINTEL", OpenCL_std, CoopMatr, 2, 2, OpCooperativeMatrixGetElementCoordINTEL>;
+// Arbitrary Precision Floating Point builtin records:
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatGTINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatGTINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatGEINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatGEINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLTINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatLTINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLEINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatLEINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatEQINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatEQINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatRecipINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatRecipINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCbrtINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCbrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatHypotINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatHypotINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSqrtINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLogINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatLogINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLog2INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatLog2INTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLog10INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatLog10INTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLog1pINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatLog1pINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatExpINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatExpINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatExp2INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatExp2INTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatExp10INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatExp10INTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatExpm1INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatExpm1INTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSinINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSinINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCosINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSinCosINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSinCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSinPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSinPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCosPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSinCosPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSinCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatAddINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatAddINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSubINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatSubINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatMulINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatMulINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatDivINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatDivINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatRSqrtINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatRSqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatASinINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatASinINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatASinPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatASinPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatACosINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatACosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatACosPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatACosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatATanINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatATanINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatATanPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatATanPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatATan2INTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatATan2INTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatPowINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatPowINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatPowRINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatPowRINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatPowNINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatPowNINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCastINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCastINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCastFromIntINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCastFromIntINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCastToIntINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCastToIntINTEL>;
+
// SPV_INTEL_bindless_images builtin records:
defm : DemangledNativeBuiltin<"__spirv_ConvertHandleToImageINTEL", OpenCL_std, BindlessINTEL, 1, 1, OpConvertHandleToImageINTEL>;
defm : DemangledNativeBuiltin<"__spirv_ConvertHandleToSamplerINTEL", OpenCL_std, BindlessINTEL, 1, 1, OpConvertHandleToSamplerINTEL>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 56cbd9414c9ee..1d56bcdfd7471 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -97,8 +97,10 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
SPIRV::Extension::Extension::
SPV_INTEL_subgroup_matrix_multiply_accumulate},
{"SPV_INTEL_ternary_bitwise_function",
- SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
-
+ SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
+ {"SPV_INTEL_arbitrary_precision_floating_point",
+ SPIRV::Extension::Extension::SPV_INTEL_arbitrary_precision_floating_point}};
+
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
std::set<SPIRV::Extension::Extension> &Vals) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 6d8c84945d7d4..32b2485044d51 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -936,3 +936,106 @@ def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops),
// SPV_INTEL_ternary_bitwise_function
def OpBitwiseFunctionINTEL: Op<6242, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c, ID:$lut_index),
"$res = OpBitwiseFunctionINTEL $type $a $b $c $lut_index">;
+
+// SPV_INTEL_arbitrary_precision_floating_point
+def OpArbitraryFloatGTINTEL: Op<5850, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb),
+ "$res = OpArbitraryFloatGTINTEL $type $A $Ma $B $Mb">;
+def OpArbitraryFloatGEINTEL: Op<5851, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb),
+ "$res = OpArbitraryFloatGEINTEL $type $A $Ma $B $Mb">;
+def OpArbitraryFloatLTINTEL: Op<5852, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb),
+ "$res = OpArbitraryFloatLTINTEL $type $A $Ma $B $Mb">;
+def OpArbitraryFloatLEINTEL: Op<5853, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb),
+ "$res = OpArbitraryFloatLEINTEL $type $A $Ma $B $Mb">;
+def OpArbitraryFloatEQINTEL: Op<5854, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb),
+ "$res = OpArbitraryFloatEQINTEL $type $A $Ma $B $Mb">;
+def OpArbitraryFloatRecipINTEL: Op<5855, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatRecipINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatCbrtINTEL: Op<5857, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatCbrtINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatHypotINTEL: Op<5858, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, ID:$B, i32imm:$Mb, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatHypotINTEL $type $A $Ma $B $Mb $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatSqrtINTEL: Op<5859, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatSqrtINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatLogINTEL: Op<5860, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatLogINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatLog2INTEL: Op<5861, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatLog2INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatLog10INTEL: Op<5862, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatLog10INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatLog1pINTEL: Op<5863, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatLog1pINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatExpINTEL: Op<5864, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatExpINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatExp2INTEL: Op<5865, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatExp2INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatExp10INTEL: Op<5866, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatExp10INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatExpm1INTEL: Op<5867, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatExpm1INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatSinINTEL: Op<5868, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatSinINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatCosINTEL: Op<5869, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatCosINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatSinCosINTEL: Op<5870, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatSinCosINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatSinPiINTEL: Op<5871, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatSinPiINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatCosPiINTEL: Op<5872, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatCosPiINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatSinCosPiINTEL: Op<5840, (outs ID:$res),
+ (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy),
+ "$res = OpArbitraryFloatSinCosPiINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">;
+def OpArbitraryFloatAddINTEL: Op<5846, (outs ID:$res),
+ (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatAddINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatSubINTEL: Op<5847, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatSubINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatMulINTEL: Op<5848, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatMulINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatDivINTEL: Op<5849, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatDivINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatRSqrtINTEL: Op<5856, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatRSqrtINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatASinINTEL: Op<5873, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatASinINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatASinPiINTEL: Op<5874, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatASinPiINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatACosINTEL : Op<5875, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatACosINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatACosPiINTEL: Op<5876, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatACosPiINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatATanINTEL: Op<5877, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatATanINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatATanPiINTEL: Op<5878, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatATanPiINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatATan2INTEL: Op<5879, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatATan2INTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatPowINTEL: Op<5880, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatPowINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatPowRINTEL: Op<5881, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i1imm:$src2_sign, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatPowRINTEL $type $src $src_mwidth $src2 $src2_sign $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatPowNINTEL: Op<5882, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i1imm:$src2_sign, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode),
+ "$res = OpArbitraryFloatPowNINTEL $type $src $src_mwidth $src2 $src2_sign $res_mwidth $subnorm $fproundingmode $roundaccuracymode">;
+def OpArbitraryFloatCastINTEL: Op<5841, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundignAccuracy),
+ "$res = OpArbitraryFloatCastINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundignAccuracy">;
+def OpArbitraryFloatCastFromIntINTEL: Op<5842, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$res_mwidth, i32imm:$fromsign, i32imm:$subnormalmode, i32imm:$fproundingmode, i32imm:$roundignAccuracy),
+ "$res = OpArbitraryFloatCastFromIntINTEL $type $src $res_mwidth $fromsign $subnormalmode $fproundingmode $roundignAccuracy">;
+def OpArbitraryFloatCastToIntINTEL: Op<5838, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$res_mwidth, i32imm:$tosign, i32imm:$subnormalmode, i32imm:$fproundingmode, i32imm:$roundignAccuracy),
+ "$res = OpArbitraryFloatCastToIntINTEL $type $src $res_mwidth $tosign $subnormalmode $fproundingmode $roundignAccuracy">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 6d2ecd563d200..ceb68553efcc2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1824,7 +1824,57 @@ void addInstrRequirements(const MachineInstr &MI,
Reqs.addCapability(SPIRV::Capability::TernaryBitwiseFunctionINTEL);
break;
}
-
+ case SPIRV::OpArbitraryFloatEQINTEL:
+ case SPIRV::OpArbitraryFloatGEINTEL:
+ case SPIRV::OpArbitraryFloatGTINTEL:
+ case SPIRV::OpArbitraryFloatLEINTEL:
+ case SPIRV::OpArbitraryFloatLTINTEL:
+ case SPIRV::OpArbitraryFloatCbrtINTEL:
+ case SPIRV::OpArbitraryFloatCosINTEL:
+ case SPIRV::OpArbitraryFloatCosPiINTEL:
+ case SPIRV::OpArbitraryFloatExp10INTEL:
+ case SPIRV::OpArbitraryFloatExp2INTEL:
+ case SPIRV::OpArbitraryFloatExpINTEL:
+ case SPIRV::OpArbitraryFloatExpm1INTEL:
+ case SPIRV::OpArbitraryFloatHypotINTEL:
+ case SPIRV::OpArbitraryFloatLog10INTEL:
+ case SPIRV::OpArbitraryFloatLog1pINTEL:
+ case SPIRV::OpArbitraryFloatLog2INTEL:
+ case SPIRV::OpArbitraryFloatLogINTEL:
+ case SPIRV::OpArbitraryFloatRecipINTEL:
+ case SPIRV::OpArbitraryFloatSinCosINTEL:
+ case SPIRV::OpArbitraryFloatSinCosPiINTEL:
+ case SPIRV::OpArbitraryFloatSinINTEL:
+ case SPIRV::OpArbitraryFloatSinPiINTEL:
+ case SPIRV::OpArbitraryFloatSqrtINTEL:
+ case SPIRV::OpArbitraryFloatACosINTEL:
+ case SPIRV::OpArbitraryFloatACosPiINTEL:
+ case SPIRV::OpArbitraryFloatAddINTEL:
+ case SPIRV::OpArbitraryFloatASinINTEL:
+ case SPIRV::OpArbitraryFloatASinPiINTEL:
+ case SPIRV::OpArbitraryFloatATan2INTEL:
+ case SPIRV::OpArbitraryFloatATanINTEL:
+ case SPIRV::OpArbitraryFloatATanPiINTEL:
+ case SPIRV::OpArbitraryFloatCastFromIntINTEL:
+ case SPIRV::OpArbitraryFloatCastINTEL:
+ case SPIRV::OpArbitraryFloatCastToIntINTEL:
+ case SPIRV::OpArbitraryFloatDivINTEL:
+ case SPIRV::OpArbitraryFloatMulINTEL:
+ case SPIRV::OpArbitraryFloatPowINTEL:
+ case SPIRV::OpArbitraryFloatPowNINTEL:
+ case SPIRV::OpArbitraryFloatPowRINTEL:
+ case SPIRV::OpArbitraryFloatRSqrtINTEL:
+ case SPIRV::OpArbitraryFloatSubINTEL:
+ if (!ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_floating_point))
+ report_fatal_error(
+ "Floating point instructions can't be translated correctly without "
+ "enabled SPV_INTEL_arbitrary_precision_floating_point extension!",
+ false);
+ Reqs.addExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_floating_point);
+ Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFloatingPointINTEL);
+ break;
default:
break;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index cc32200a0a261..81739cf7db64b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -315,6 +315,7 @@ defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
defm SPV_INTEL_fp_max_error : ExtensionOperand<119>;
defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
defm SPV_INTEL_subgroup_matrix_multiply_accumulate : ExtensionOperand<121>;
+defm SPV_INTEL_arbitrary_precision_floating_point: ExtensionOperand<122>;
//===----------------------------------------------------------------------===//
// Multiclass used to define Capabilities enum values and at the same time
@@ -517,6 +518,7 @@ defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory
defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
defm SubgroupMatrixMultiplyAccumulateINTEL : CapabilityOperand<6236, 0, 0, [SPV_INTEL_subgroup_matrix_multiply_accumulate], []>;
+defm ArbitraryPrecisionFloatingPointINTEL : CapabilityOperand<5845, 0, 0,[SPV_INTEL_arbitrary_precision_floating_point], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/capability-arbitrary-precision-floating-point.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/capability-arbitrary-precision-floating-point.ll
new file mode 100644
index 0000000000000..fe568cd5951a1
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/capability-arbitrary-precision-floating-point.ll
@@ -0,0 +1,1237 @@
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_floating_point,+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
+
+; CHECK: OpCapability Kernel
+; CHECK: OpCapability ArbitraryPrecisionFloatingPointINTEL
+; CHECK: OpCapability ArbitraryPrecisionIntegersINTEL
+; CHECK: OpExtension "SPV_INTEL_arbitrary_precision_floating_point"
+; CHECK: OpExtension "SPV_INTEL_arbitrary_precision_integers"
+
+; CHECK-DAG: %[[Ty_8:[0-9]+]] = OpTypeInt 8 0
+; CHECK-DAG: %[[Ty_40:[0-9]+]] = OpTypeInt 40 0
+; CHECK-DAG: %[[Ty_43:[0-9]+]] = OpTypeInt 43 0
+; CHECK-DAG: %[[Ty_25:[0-9]+]] = OpTypeInt 25 0
+; CHECK-DAG: %[[Ty_23:[0-9]+]] = OpTypeInt 23 0
+; CHECK-DAG: %[[Ty_30:[0-9]+]] = OpTypeInt 30 0
+; CHECK-DAG: %[[Ty_13:[0-9]+]] = OpTypeInt 13 0
+; CHECK-DAG: %[[Ty_15:[0-9]+]] = OpTypeInt 15 0
+; CHECK-DAG: %[[Ty_14:[0-9]+]] = OpTypeInt 14 0
+; CHECK-DAG: %[[Ty_9:[0-9]+]] = OpTypeInt 9 0
+; CHECK-DAG: %[[Ty_11:[0-9]+]] = OpTypeInt 11 0
+; CHECK-DAG: %[[Ty_51:[0-9]+]] = OpTypeInt 51 0
+; CHECK-DAG: %[[Ty_16:[0-9]+]] = OpTypeInt 16 0
+; CHECK-DAG: %[[Ty_18:[0-9]+]] = OpTypeInt 18 0
+; CHECK-DAG: %[[Ty_63:[0-9]+]] = OpTypeInt 63 0
+; CHECK-DAG: %[[Ty_47:[0-9]+]] = OpTypeInt 47 0
+; CHECK-DAG: %[[Ty_5:[0-9]+]] = OpTypeInt 5 0
+; CHECK-DAG: %[[Ty_7:[0-9]+]] = OpTypeInt 7 0
+; CHECK-DAG: %[[Ty_55:[0-9]+]] = OpTypeInt 55 0
+; CHECK-DAG: %[[Ty_20:[0-9]+]] = OpTypeInt 20 0
+; CHECK-DAG: %[[Ty_39:[0-9]+]] = OpTypeInt 39 0
+; CHECK-DAG: %[[Ty_32:[0-9]+]] = OpTypeInt 32 0
+; CHECK-DAG: %[[Ty_34:[0-9]+]] = OpTypeInt 34 0
+; CHECK-DAG: %[[Ty_2:[0-9]+]] = OpTypeInt 2 0
+; CHECK-DAG: %[[Ty_41:[0-9]+]] = OpTypeInt 41 0
+; CHECK-DAG: %[[Ty_42:[0-9]+]] = OpTypeInt 42 0
+; CHECK-DAG: %[[Ty_17:[0-9]+]] = OpTypeInt 17 0
+; CHECK-DAG: %[[Ty_50:[0-9]+]] = OpTypeInt 50 0
+; CHECK-DAG: %[[Ty_38:[0-9]+]] = OpTypeInt 38 0
+; CHECK-DAG: %[[Ty_10:[0-9]+]] = OpTypeInt 10 0
+; CHECK-DAG: %[[Ty_48:[0-9]+]] = OpTypeInt 48 0
+; CHECK-DAG: %[[Ty_49:[0-9]+]] = OpTypeInt 49 0
+; CHECK-DAG: %[[Ty_3:[0-9]+]] = OpTypeInt 3 0
+; CHECK-DAG: %[[Ty_64:[0-9]+]] = OpTypeInt 64 0
+; CHECK-DAG: %[[Ty_62:[0-9]+]] = OpTypeInt 62 0
+; CHECK-DAG: %[[Ty_4:[0-9]+]] = OpTypeInt 4 0
+; CHECK-DAG: %[[Ty_27:[0-9]+]] = OpTypeInt 27 0
+; CHECK-DAG: %[[Ty_59:[0-9]+]] = OpTypeInt 59 0
+; CHECK-DAG: %[[Ty_35:[0-9]+]] = OpTypeInt 35 0
+; CHECK-DAG: %[[Ty_44:[0-9]+]] = OpTypeInt 44 0
+; CHECK-DAG: %[[Ty_24:[0-9]+]] = OpTypeInt 24 0
+; CHECK-DAG: %[[Ty_19:[0-9]+]] = OpTypeInt 19 0
+; CHECK-DAG: %[[Ty_21:[0-9]+]] = OpTypeInt 21 0
+; CHECK-DAG: %[[Ty_54:[0-9]+]] = OpTypeInt 54 0
+; CHECK-DAG: %[[Ty_56:[0-9]+]] = OpTypeInt 56 0
+; CHECK-DAG: %[[Ty_12:[0-9]+]] = OpTypeInt 12 0
+; CHECK-DAG: %[[Ty_Bool:[0-9]+]] = OpTypeBool
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
+target triple = "spir64-unknown-linux"
+
+%"class._ZTSZ4mainE3$_0.anon" = type { i8 }
+
+; Function Attrs: norecurse
+define dso_local spir_kernel void @_ZTSZ4mainE15kernel_function() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 {
+ %1 = alloca %"class._ZTSZ4mainE3$_0.anon", align 1
+ call void @llvm.lifetime.start.p0(i64 1, ptr %1) #5
+ %2 = addrspacecast ptr %1 to ptr addrspace(4)
+ call spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %2)
+ call void @llvm.lifetime.end.p0(i64 1, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr captures(none)) #1
+
+; Function Attrs: inlinehint norecurse
+define internal spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %0) #2 align 2 {
+ %2 = alloca ptr addrspace(4), align 8
+ store ptr addrspace(4) %0, ptr %2, align 8, !tbaa !5
+ call spir_func void @_Z13ap_float_castILi11ELi28ELi9ELi30EEvv()
+ call spir_func void @_Z22ap_float_cast_from_intILi43ELi8ELi16EEvv()
+ call spir_func void @_Z20ap_float_cast_to_intILi7ELi15ELi30EEvv()
+ call spir_func void @_Z12ap_float_addILi5ELi7ELi6ELi8ELi4ELi9EEvv()
+ call spir_func void @_Z12ap_float_addILi6ELi8ELi4ELi9ELi5ELi7EEvv()
+ call spir_func void @_Z12ap_float_subILi4ELi4ELi5ELi5ELi6ELi6EEvv()
+ call spir_func void @_Z12ap_float_mulILi16ELi34ELi16ELi34ELi16ELi34EEvv()
+ call spir_func void @_Z12ap_float_divILi4ELi11ELi4ELi11ELi5ELi12EEvv()
+ call spir_func void @_Z11ap_float_gtILi20ELi42ELi21ELi41EEvv()
+ call spir_func void @_Z11ap_float_geILi19ELi27ELi19ELi27EEvv()
+ call spir_func void @_Z11ap_float_ltILi2ELi2ELi3ELi3EEvv()
+ call spir_func void @_Z11ap_float_leILi27ELi27ELi26ELi28EEvv()
+ call spir_func void @_Z11ap_float_eqILi7ELi12ELi7ELi7EEvv()
+ call spir_func void @_Z14ap_float_recipILi9ELi29ELi9ELi29EEvv()
+ call spir_func void @_Z14ap_float_rsqrtILi12ELi19ELi13ELi20EEvv()
+ call spir_func void @_Z13ap_float_cbrtILi0ELi1ELi0ELi1EEvv()
+ call spir_func void @_Z14ap_float_hypotILi20ELi20ELi21ELi21ELi19ELi22EEvv()
+ call spir_func void @_Z13ap_float_sqrtILi7ELi7ELi8ELi8EEvv()
+ call spir_func void @_Z12ap_float_logILi30ELi19ELi19ELi30EEvv()
+ call spir_func void @_Z13ap_float_log2ILi17ELi20ELi18ELi19EEvv()
+ call spir_func void @_Z14ap_float_log10ILi4ELi3ELi4ELi5EEvv()
+ call spir_func void @_Z14ap_float_log1pILi17ELi30ELi18ELi30EEvv()
+ call spir_func void @_Z12ap_float_expILi16ELi25ELi16ELi25EEvv()
+ call spir_func void @_Z13ap_float_exp2ILi1ELi1ELi2ELi2EEvv()
+ call spir_func void @_Z14ap_float_exp10ILi8ELi16ELi8ELi16EEvv()
+ call spir_func void @_Z14ap_float_expm1ILi21ELi42ELi20ELi41EEvv()
+ call spir_func void @_Z12ap_float_sinILi14ELi15ELi16ELi17EEvv()
+ call spir_func void @_Z12ap_float_cosILi1ELi2ELi2ELi1EEvv()
+ call spir_func void @_Z15ap_float_sincosILi8ELi18ELi10ELi20EEvv()
+ call spir_func void @_Z14ap_float_sinpiILi3ELi6ELi6ELi6EEvv()
+ call spir_func void @_Z14ap_float_cospiILi18ELi40ELi18ELi40EEvv()
+ call spir_func void @_Z17ap_float_sincospiILi9ELi20ELi11ELi20EEvv()
+ call spir_func void @_Z13ap_float_asinILi2ELi4ELi2ELi8EEvv()
+ call spir_func void @_Z15ap_float_asinpiILi11ELi23ELi11ELi23EEvv()
+ call spir_func void @_Z13ap_float_acosILi4ELi9ELi3ELi10EEvv()
+ call spir_func void @_Z15ap_float_acospiILi2ELi5ELi3ELi4EEvv()
+ call spir_func void @_Z13ap_float_atanILi12ELi31ELi12ELi31EEvv()
+ call spir_func void @_Z15ap_float_atanpiILi1ELi38ELi1ELi32EEvv()
+ call spir_func void @_Z14ap_float_atan2ILi7ELi16ELi7ELi17ELi8ELi18EEvv()
+ call spir_func void @_Z12ap_float_powILi8ELi8ELi9ELi9ELi10ELi10EEvv()
+ call spir_func void @_Z13ap_float_powrILi18ELi35ELi19ELi35ELi20ELi35EEvv()
+ call spir_func void @_Z13ap_float_pownILi4ELi7ELi10ELi5ELi9EEvv()
+ call spir_func void @_Z15ap_float_sincosILi8ELi18ELi10ELi20EEvv_()
+ call spir_func void @_Z14ap_float_atan2ILi7ELi16ELi7ELi17ELi8ELi18EEvv_()
+ call spir_func void @_Z13ap_float_pownILi64ELi7ELi10ELi5ELi9EEvv()
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr captures(none)) #1
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_castILi11ELi28ELi9ELi30EEvv() #3 {
+ %1 = alloca i40, align 8
+ %2 = alloca i40, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i40, ptr %1, align 8, !tbaa !9
+ %4 = call spir_func i40 @_Z31__spirv_ArbitraryFloatCastINTELILi40ELi40EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i40 %3, i32 28, i32 30, i32 0, i32 2, i32 1) #5
+; CHECK: %[[LoadVar:[0-9]+]] = OpLoad %[[Ty_40]] %[[SourceVar:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[CastResult:[0-9]+]] = OpArbitraryFloatCastINTEL %[[Ty_40]] %[[LoadVar]] 28 30 0 2 1
+ store i40 %4, ptr %2, align 8, !tbaa !9
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z22ap_float_cast_from_intILi43ELi8ELi16EEvv() #3 {
+ %1 = alloca i43, align 8
+ %2 = alloca i25, align 4
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
+ %3 = load i43, ptr %1, align 8, !tbaa !11
+ %4 = call spir_func signext i25 @_Z38__spirv_ArbitraryFloatCastFromIntINTELILi43ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i43 %3, i32 16, i1 zeroext false, i32 0, i32 2, i32 1) #5
+; CHECK: %[[LoadVar:[0-9]+]] = OpLoad %[[Ty_43]] %[[SourceVar:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[CastResult:[0-9]+]] = OpArbitraryFloatCastFromIntINTEL %[[Ty_25]] %[[LoadVar]] 16 0 0 2 1
+ store i25 %4, ptr %2, align 4, !tbaa !13
+ call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z20ap_float_cast_to_intILi7ELi15ELi30EEvv() #3 {
+ %1 = alloca i23, align 4
+ %2 = alloca i30, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
+ %3 = load i23, ptr %1, align 4, !tbaa !15
+ %4 = call spir_func signext i30 @_Z36__spirv_ArbitraryFloatCastToIntINTELILi23ELi30EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i23 signext %3, i32 15, i1 zeroext true, i32 0, i32 2, i32 1) #5
+; CHECK: %[[LoadVar:[0-9]+]] = OpLoad %[[Ty_23]] %[[SourceVar:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[CastResult:[0-9]+]] = OpArbitraryFloatCastToIntINTEL %[[Ty_30]] %[[LoadVar]] 15 1 0 2 1
+ store i30 %4, ptr %2, align 4, !tbaa !17
+ call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_addILi5ELi7ELi6ELi8ELi4ELi9EEvv() #3 {
+ %1 = alloca i13, align 2
+ %2 = alloca i13, align 2
+ %3 = alloca i15, align 2
+ %4 = alloca i15, align 2
+ %5 = alloca i14, align 2
+ %6 = alloca i14, align 2
+ call void @llvm.lifetime.start.p0(i64 2, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %3) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %4) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %5) #5
+ %7 = load i13, ptr %1, align 2, !tbaa !19
+ %8 = load i15, ptr %3, align 2, !tbaa !21
+ %9 = call spir_func signext i14 @_Z30__spirv_ArbitraryFloatAddINTELILi13ELi15ELi14EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i13 signext %7, i32 7, i15 signext %8, i32 8, i32 9, i32 0, i32 2, i32 1) #5
+; CHECK: %[[AddOp1:[0-9]+]] = OpLoad %[[Ty_13]] %[[Src1:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[AddOp2:[0-9]+]] = OpLoad %[[Ty_15]] %[[Src2:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[AddResult:[0-9]+]] = OpArbitraryFloatAddINTEL %[[Ty_14]] %[[AddOp1]] 7 %[[AddOp2]] 8 9 0 2 1
+ store i14 %9, ptr %5, align 2, !tbaa !23
+ call void @llvm.lifetime.start.p0(i64 2, ptr %6) #5
+ %10 = load i13, ptr %2, align 2, !tbaa !19
+ %11 = load i15, ptr %4, align 2, !tbaa !21
+ %12 = call spir_func signext i14 @_Z30__spirv_ArbitraryFloatAddINTELILi13ELi15ELi14EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i13 signext %10, i32 7, i15 signext %11, i32 8, i32 9, i32 0, i32 2, i32 1) #5
+; CHECK: %[[AddOp1:[0-9]+]] = OpLoad %[[Ty_13]] %[[Src1:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[AddOp2:[0-9]+]] = OpLoad %[[Ty_15]] %[[Src2:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[AddResult:[0-9]+]] = OpArbitraryFloatAddINTEL %[[Ty_14]] %[[AddOp1]] 7 %[[AddOp2]] 8 9 0 2 1
+ store i14 %12, ptr %6, align 2, !tbaa !23
+ call void @llvm.lifetime.end.p0(i64 2, ptr %6) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %5) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %4) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_addILi6ELi8ELi4ELi9ELi5ELi7EEvv() #3 {
+ %1 = alloca i15, align 2
+ %2 = alloca i15, align 2
+ %3 = alloca i14, align 2
+ %4 = alloca i14, align 2
+ %5 = alloca i13, align 2
+ %6 = alloca i13, align 2
+ call void @llvm.lifetime.start.p0(i64 2, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %3) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %4) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %5) #5
+ %7 = load i15, ptr %1, align 2, !tbaa !21
+ %8 = load i14, ptr %3, align 2, !tbaa !23
+ %9 = call spir_func signext i13 @_Z30__spirv_ArbitraryFloatAddINTELILi15ELi14ELi13EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i15 signext %7, i32 8, i14 signext %8, i32 9, i32 7, i32 0, i32 2, i32 1) #5
+; CHECK: %[[AddOp1:[0-9]+]] = OpLoad %[[Ty_15]] %[[Src1:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[AddOp2:[0-9]+]] = OpLoad %[[Ty_14]] %[[Src2:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[AddResult:[0-9]+]] = OpArbitraryFloatAddINTEL %[[Ty_13]] %[[AddOp1]] 8 %[[AddOp2]] 9 7 0 2 1
+ store i13 %9, ptr %5, align 2, !tbaa !19
+ call void @llvm.lifetime.start.p0(i64 2, ptr %6) #5
+ %10 = load i15, ptr %2, align 2, !tbaa !21
+ %11 = load i14, ptr %4, align 2, !tbaa !23
+ %12 = call spir_func signext i13 @_Z30__spirv_ArbitraryFloatAddINTELILi15ELi14ELi13EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i15 signext %10, i32 8, i14 signext %11, i32 9, i32 7, i32 0, i32 2, i32 1) #5
+; CHECK: %[[AddOp1:[0-9]+]] = OpLoad %[[Ty_15]] %[[Add2_A2:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[AddOp2:[0-9]+]] = OpLoad %[[Ty_14]] %[[Add2_B2:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[AddResult:[0-9]+]] = OpArbitraryFloatAddINTEL %[[Ty_13]] %[[AddOp1]] 8 %[[AddOp2]] 9 7 0 2 1
+ store i13 %12, ptr %6, align 2, !tbaa !19
+ call void @llvm.lifetime.end.p0(i64 2, ptr %6) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %5) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %4) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_subILi4ELi4ELi5ELi5ELi6ELi6EEvv() #3 {
+ %1 = alloca i9, align 2
+ %2 = alloca i11, align 2
+ %3 = alloca i13, align 2
+ call void @llvm.lifetime.start.p0(i64 2, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %3) #5
+ %4 = load i9, ptr %1, align 2, !tbaa !25
+ %5 = load i11, ptr %2, align 2, !tbaa !27
+ %6 = call spir_func signext i13 @_Z30__spirv_ArbitraryFloatSubINTELILi9ELi11ELi13EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i9 signext %4, i32 4, i11 signext %5, i32 5, i32 6, i32 0, i32 2, i32 1) #5
+; CHECK: %[[SubOp1:[0-9]+]] = OpLoad %[[Ty_9]] %[[Sub_A:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[SubOp2:[0-9]+]] = OpLoad %[[Ty_11]] %[[Sub_B:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[SubResult:[0-9]+]] = OpArbitraryFloatSubINTEL %[[Ty_13]] %[[SubOp1]] 4 %[[SubOp2]] 5 6 0 2 1
+ store i13 %6, ptr %3, align 2, !tbaa !19
+ call void @llvm.lifetime.end.p0(i64 2, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_mulILi16ELi34ELi16ELi34ELi16ELi34EEvv() #3 {
+ %1 = alloca i51, align 8
+ %2 = alloca i51, align 8
+ %3 = alloca i51, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %3) #5
+ %4 = load i51, ptr %1, align 8, !tbaa !29
+ %5 = load i51, ptr %2, align 8, !tbaa !29
+ %6 = call spir_func i51 @_Z30__spirv_ArbitraryFloatMulINTELILi51ELi51ELi51EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i51 %4, i32 34, i51 %5, i32 34, i32 34, i32 0, i32 2, i32 1) #5
+; CHECK: %[[MulOp1:[0-9]+]] = OpLoad %[[Ty_51]] %[[Mul_A:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[MulOp2:[0-9]+]] = OpLoad %[[Ty_51]] %[[Mul_B:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[MulResult:[0-9]+]] = OpArbitraryFloatMulINTEL %[[Ty_51]] %[[MulOp1]] 34 %[[MulOp2]] 34 34 0 2 1
+ store i51 %6, ptr %3, align 8, !tbaa !29
+ call void @llvm.lifetime.end.p0(i64 8, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_divILi4ELi11ELi4ELi11ELi5ELi12EEvv() #3 {
+ %1 = alloca i16, align 2
+ %2 = alloca i16, align 2
+ %3 = alloca i18, align 4
+ call void @llvm.lifetime.start.p0(i64 2, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
+ %4 = load i16, ptr %1, align 2, !tbaa !31
+ %5 = load i16, ptr %2, align 2, !tbaa !31
+ %6 = call spir_func signext i18 @_Z30__spirv_ArbitraryFloatDivINTELILi16ELi16ELi18EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i16 signext %4, i32 11, i16 signext %5, i32 11, i32 12, i32 0, i32 2, i32 1) #5
+; CHECK: %[[DivOp1:[0-9]+]] = OpLoad %[[Ty_16]] %[[Div_A:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[DivOp2:[0-9]+]] = OpLoad %[[Ty_16]] %[[Div_B:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[DivResult:[0-9]+]] = OpArbitraryFloatDivINTEL %[[Ty_18]] %[[DivOp1]] 11 %[[DivOp2]] 11 12 0 2 1
+ store i18 %6, ptr %3, align 4, !tbaa !33
+ call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z11ap_float_gtILi20ELi42ELi21ELi41EEvv() #3 {
+ %1 = alloca i63, align 8
+ %2 = alloca i63, align 8
+ %3 = alloca i8, align 1
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %3) #5
+ %4 = load i63, ptr %1, align 8, !tbaa !35
+ %5 = load i63, ptr %2, align 8, !tbaa !35
+ %6 = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatGTINTELILi63ELi63EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i63 %4, i32 42, i63 %5, i32 41) #5
+; CHECK: %[[GTOp1:[0-9]+]] = OpLoad %[[Ty_63]] %[[GT_A:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[GTOp2:[0-9]+]] = OpLoad %[[Ty_63]] %[[GT_B:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[GTResult:[0-9]+]] = OpArbitraryFloatGTINTEL %[[Ty_Bool]] %[[GTOp1]] 42 %[[GTOp2]] 41
+ %7 = zext i1 %6 to i8
+ store i8 %7, ptr %3, align 1, !tbaa !37
+ call void @llvm.lifetime.end.p0(i64 1, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z11ap_float_geILi19ELi27ELi19ELi27EEvv() #3 {
+ %1 = alloca i47, align 8
+ %2 = alloca i47, align 8
+ %3 = alloca i8, align 1
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %3) #5
+ %4 = load i47, ptr %1, align 8, !tbaa !39
+ %5 = load i47, ptr %2, align 8, !tbaa !39
+ %6 = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatGEINTELILi47ELi47EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i47 %4, i32 27, i47 %5, i32 27) #5
+; CHECK: %[[GE_A1:[0-9]+]] = OpLoad %[[Ty_47]] %[[GE_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[GE_B1:[0-9]+]] = OpLoad %[[Ty_47]] %[[GE_BId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[GEResult:[0-9]+]] = OpArbitraryFloatGEINTEL %[[Ty_Bool]] %[[GE_A1]] 27 %[[GE_B1]] 27
+ %7 = zext i1 %6 to i8
+ store i8 %7, ptr %3, align 1, !tbaa !37
+ call void @llvm.lifetime.end.p0(i64 1, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z11ap_float_ltILi2ELi2ELi3ELi3EEvv() #3 {
+ %1 = alloca i5, align 1
+ %2 = alloca i7, align 1
+ %3 = alloca i8, align 1
+ call void @llvm.lifetime.start.p0(i64 1, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %3) #5
+ %4 = load i5, ptr %1, align 1, !tbaa !41
+ %5 = load i7, ptr %2, align 1, !tbaa !43
+ %6 = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatLTINTELILi5ELi7EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i5 signext %4, i32 2, i7 signext %5, i32 3) #5
+; CHECK: %[[LT_A1:[0-9]+]] = OpLoad %[[Ty_5]] %[[LT_AId:[0-9]+]] Aligned 1
+; CHECK-NEXT: %[[LT_B1:[0-9]+]] = OpLoad %[[Ty_7]] %[[LT_BId:[0-9]+]] Aligned 1
+; CHECK-NEXT: %[[LTResult:[0-9]+]] = OpArbitraryFloatLTINTEL %[[Ty_Bool]] %[[LT_A1]] 2 %[[LT_B1]] 3
+ %7 = zext i1 %6 to i8
+ store i8 %7, ptr %3, align 1, !tbaa !37
+ call void @llvm.lifetime.end.p0(i64 1, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z11ap_float_leILi27ELi27ELi26ELi28EEvv() #3 {
+ %1 = alloca i55, align 8
+ %2 = alloca i55, align 8
+ %3 = alloca i8, align 1
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %3) #5
+ %4 = load i55, ptr %1, align 8, !tbaa !45
+ %5 = load i55, ptr %2, align 8, !tbaa !45
+ %6 = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatLEINTELILi55ELi55EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i55 %4, i32 27, i55 %5, i32 28) #5
+; CHECK: %[[LE_A1:[0-9]+]] = OpLoad %[[Ty_55]] %[[LE_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[LE_B1:[0-9]+]] = OpLoad %[[Ty_55]] %[[LE_BId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[LEResult:[0-9]+]] = OpArbitraryFloatLEINTEL %[[Ty_Bool]] %[[LE_A1]] 27 %[[LE_B1]] 28
+ %7 = zext i1 %6 to i8
+ store i8 %7, ptr %3, align 1, !tbaa !37
+ call void @llvm.lifetime.end.p0(i64 1, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z11ap_float_eqILi7ELi12ELi7ELi7EEvv() #3 {
+ %1 = alloca i20, align 4
+ %2 = alloca i15, align 2
+ %3 = alloca i8, align 1
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %3) #5
+ %4 = load i20, ptr %1, align 4, !tbaa !47
+ %5 = load i15, ptr %2, align 2, !tbaa !21
+ %6 = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatEQINTELILi20ELi15EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i20 signext %4, i32 12, i15 signext %5, i32 7) #5
+; CHECK: %[[EQ_A1:[0-9]+]] = OpLoad %[[Ty_20]] %[[EQ_AId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[EQ_B1:[0-9]+]] = OpLoad %[[Ty_15]] %[[EQ_BId:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[EQResult:[0-9]+]] = OpArbitraryFloatEQINTEL %[[Ty_Bool]] %[[EQ_A1]] 12 %[[EQ_B1]] 7
+ %7 = zext i1 %6 to i8
+ store i8 %7, ptr %3, align 1, !tbaa !37
+ call void @llvm.lifetime.end.p0(i64 1, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_recipILi9ELi29ELi9ELi29EEvv() #3 {
+ %1 = alloca i39, align 8
+ %2 = alloca i39, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i39, ptr %1, align 8, !tbaa !49
+ %4 = call spir_func i39 @_Z32__spirv_ArbitraryFloatRecipINTELILi39ELi39EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i39 %3, i32 29, i32 29, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Recip_A1:[0-9]+]] = OpLoad %[[Ty_39]] %[[Recip_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[RecipResult:[0-9]+]] = OpArbitraryFloatRecipINTEL %[[Ty_39]] %[[Recip_A1]] 29 29 0 2 1
+ store i39 %4, ptr %2, align 8, !tbaa !49
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_rsqrtILi12ELi19ELi13ELi20EEvv() #3 {
+ %1 = alloca i32, align 4
+ %2 = alloca i34, align 8
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i32, ptr %1, align 4, !tbaa !51
+ %4 = call spir_func i34 @_Z32__spirv_ArbitraryFloatRSqrtINTELILi32ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i32 %3, i32 19, i32 20, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Rsqrt_A1:[0-9]+]] = OpLoad %[[Ty_32]] %[[Rsqrt_AId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[RsqrtResult:[0-9]+]] = OpArbitraryFloatRSqrtINTEL %[[Ty_34]] %[[Rsqrt_A1]] 19 20 0 2 1
+ store i34 %4, ptr %2, align 8, !tbaa !53
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_cbrtILi0ELi1ELi0ELi1EEvv() #3 {
+ %1 = alloca i2, align 1
+ %2 = alloca i2, align 1
+ call void @llvm.lifetime.start.p0(i64 1, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %2) #5
+ %3 = load i2, ptr %1, align 1, !tbaa !55
+ %4 = call spir_func signext i2 @_Z31__spirv_ArbitraryFloatCbrtINTELILi2ELi2EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i2 signext %3, i32 1, i32 1, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Cbrt_A1:[0-9]+]] = OpLoad %[[Ty_2]] %[[Cbrt_AId:[0-9]+]] Aligned 1
+; CHECK-NEXT: %[[CbrtResult:[0-9]+]] = OpArbitraryFloatCbrtINTEL %[[Ty_2]] %[[Cbrt_A1]] 1 1 0 2 1
+ store i2 %4, ptr %2, align 1, !tbaa !55
+ call void @llvm.lifetime.end.p0(i64 1, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_hypotILi20ELi20ELi21ELi21ELi19ELi22EEvv() #3 {
+ %1 = alloca i41, align 8
+ %2 = alloca i43, align 8
+ %3 = alloca i42, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %3) #5
+ %4 = load i41, ptr %1, align 8, !tbaa !57
+ %5 = load i43, ptr %2, align 8, !tbaa !11
+ %6 = call spir_func i42 @_Z32__spirv_ArbitraryFloatHypotINTELILi41ELi43ELi42EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i41 %4, i32 20, i43 %5, i32 21, i32 22, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Hypot_A1:[0-9]+]] = OpLoad %[[Ty_41]] %[[Hypot_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[Hypot_B1:[0-9]+]] = OpLoad %[[Ty_43]] %[[Hypot_BId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[HypotResult:[0-9]+]] = OpArbitraryFloatHypotINTEL %[[Ty_42]] %[[Hypot_A1]] 20 %[[Hypot_B1]] 21 22 0 2 1
+ store i42 %6, ptr %3, align 8, !tbaa !59
+ call void @llvm.lifetime.end.p0(i64 8, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_sqrtILi7ELi7ELi8ELi8EEvv() #3 {
+ %1 = alloca i15, align 2
+ %2 = alloca i17, align 4
+ call void @llvm.lifetime.start.p0(i64 2, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
+ %3 = load i15, ptr %1, align 2, !tbaa !21
+ %4 = call spir_func signext i17 @_Z31__spirv_ArbitraryFloatSqrtINTELILi15ELi17EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i15 signext %3, i32 7, i32 8, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Sqrt_A1:[0-9]+]] = OpLoad %[[Ty_15]] %[[Sqrt_AId:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[SqrtResult:[0-9]+]] = OpArbitraryFloatSqrtINTEL %[[Ty_17]] %[[Sqrt_A1]] 7 8 0 2 1
+ store i17 %4, ptr %2, align 4, !tbaa !61
+ call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_logILi30ELi19ELi19ELi30EEvv() #3 {
+ %1 = alloca i50, align 8
+ %2 = alloca i50, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i50, ptr %1, align 8, !tbaa !63
+ %4 = call spir_func i50 @_Z30__spirv_ArbitraryFloatLogINTELILi50ELi50EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i50 %3, i32 19, i32 30, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Log_A1:[0-9]+]] = OpLoad %[[Ty_50]] %[[Log_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[LogResult:[0-9]+]] = OpArbitraryFloatLogINTEL %[[Ty_50]] %[[Log_A1]] 19 30 0 2 1
+ store i50 %4, ptr %2, align 8, !tbaa !63
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_log2ILi17ELi20ELi18ELi19EEvv() #3 {
+ %1 = alloca i38, align 8
+ %2 = alloca i38, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i38, ptr %1, align 8, !tbaa !65
+ %4 = call spir_func i38 @_Z31__spirv_ArbitraryFloatLog2INTELILi38ELi38EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i38 %3, i32 20, i32 19, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Log2_A1:[0-9]+]] = OpLoad %[[Ty_38]] %[[Log2_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[Log2Result:[0-9]+]] = OpArbitraryFloatLog2INTEL %[[Ty_38]] %[[Log2_A1]] 20 19 0 2 1
+ store i38 %4, ptr %2, align 8, !tbaa !65
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_log10ILi4ELi3ELi4ELi5EEvv() #3 {
+ %1 = alloca i8, align 1
+ %2 = alloca i10, align 2
+ call void @llvm.lifetime.start.p0(i64 1, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ %3 = load i8, ptr %1, align 1, !tbaa !67
+ %4 = call spir_func signext i10 @_Z32__spirv_ArbitraryFloatLog10INTELILi8ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i8 signext %3, i32 3, i32 5, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Log10_A1:[0-9]+]] = OpLoad %[[Ty_8]] %[[Log10_AId:[0-9]+]] Aligned 1
+; CHECK-NEXT: %[[Log10Result:[0-9]+]] = OpArbitraryFloatLog10INTEL %[[Ty_10]] %[[Log10_A1]] 3 5 0 2 1
+ store i10 %4, ptr %2, align 2, !tbaa !69
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_log1pILi17ELi30ELi18ELi30EEvv() #3 {
+ %1 = alloca i48, align 8
+ %2 = alloca i49, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i48, ptr %1, align 8, !tbaa !71
+ %4 = call spir_func i49 @_Z32__spirv_ArbitraryFloatLog1pINTELILi48ELi49EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i48 %3, i32 30, i32 30, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Log1p_A1:[0-9]+]] = OpLoad %[[Ty_48]] %[[Log1p_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[Log1pResult:[0-9]+]] = OpArbitraryFloatLog1pINTEL %[[Ty_49]] %[[Log1p_A1]] 30 30 0 2 1
+ store i49 %4, ptr %2, align 8, !tbaa !73
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_expILi16ELi25ELi16ELi25EEvv() #3 {
+ %1 = alloca i42, align 8
+ %2 = alloca i42, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i42, ptr %1, align 8, !tbaa !59
+ %4 = call spir_func i42 @_Z30__spirv_ArbitraryFloatExpINTELILi42ELi42EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i42 %3, i32 25, i32 25, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Exp_A1:[0-9]+]] = OpLoad %[[Ty_42]] %[[Exp_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[ExpResult:[0-9]+]] = OpArbitraryFloatExpINTEL %[[Ty_42]] %[[Exp_A1]] 25 25 0 2 1
+ store i42 %4, ptr %2, align 8, !tbaa !59
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_exp2ILi1ELi1ELi2ELi2EEvv() #3 {
+ %1 = alloca i3, align 1
+ %2 = alloca i5, align 1
+ call void @llvm.lifetime.start.p0(i64 1, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %2) #5
+ %3 = load i3, ptr %1, align 1, !tbaa !75
+ %4 = call spir_func signext i5 @_Z31__spirv_ArbitraryFloatExp2INTELILi3ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i3 signext %3, i32 1, i32 2, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Exp2_A1:[0-9]+]] = OpLoad %[[Ty_3]] %[[Exp2_AId:[0-9]+]] Aligned 1
+; CHECK-NEXT: %[[Exp2Result:[0-9]+]] = OpArbitraryFloatExp2INTEL %[[Ty_5]] %[[Exp2_A1]] 1 2 0 2 1
+ store i5 %4, ptr %2, align 1, !tbaa !41
+ call void @llvm.lifetime.end.p0(i64 1, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_exp10ILi8ELi16ELi8ELi16EEvv() #3 {
+ %1 = alloca i25, align 4
+ %2 = alloca i25, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
+ %3 = load i25, ptr %1, align 4, !tbaa !13
+ %4 = call spir_func signext i25 @_Z32__spirv_ArbitraryFloatExp10INTELILi25ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i25 signext %3, i32 16, i32 16, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Exp10_A1:[0-9]+]] = OpLoad %[[Ty_25]] %[[Exp10_AId:[0-9]+]] Aligned
+; CHECK-NEXT: %[[Exp10Result:[0-9]+]] = OpArbitraryFloatExp10INTEL %[[Ty_25]] %[[Exp10_A1]] 16 16 0 2 1
+ store i25 %4, ptr %2, align 4, !tbaa !13
+ call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_expm1ILi21ELi42ELi20ELi41EEvv() #3 {
+ %1 = alloca i64, align 8
+ %2 = alloca i62, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i64, ptr %1, align 8, !tbaa !77
+ %4 = call spir_func i62 @_Z32__spirv_ArbitraryFloatExpm1INTELILi64ELi62EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i64 %3, i32 42, i32 41, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Expm1_A1:[0-9]+]] = OpLoad %[[Ty_64]] %[[Expm1_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[Expm1Result:[0-9]+]] = OpArbitraryFloatExpm1INTEL %[[Ty_62]] %[[Expm1_A1]] 42 41 0 2 1
+ store i62 %4, ptr %2, align 8, !tbaa !79
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_sinILi14ELi15ELi16ELi17EEvv() #3 {
+ %1 = alloca i30, align 4
+ %2 = alloca i34, align 8
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i30, ptr %1, align 4, !tbaa !17
+ %4 = call spir_func i34 @_Z30__spirv_ArbitraryFloatSinINTELILi30ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i30 signext %3, i32 15, i32 17, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Sin_A1:[0-9]+]] = OpLoad %[[Ty_30]] %[[Sin_AId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[SinResult:[0-9]+]] = OpArbitraryFloatSinINTEL %[[Ty_34]] %[[Sin_A1]] 15 17 0 2 1
+ store i34 %4, ptr %2, align 8, !tbaa !53
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_cosILi1ELi2ELi2ELi1EEvv() #3 {
+ %1 = alloca i4, align 1
+ %2 = alloca i4, align 1
+ call void @llvm.lifetime.start.p0(i64 1, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %2) #5
+ %3 = load i4, ptr %1, align 1, !tbaa !81
+ %4 = call spir_func signext i4 @_Z30__spirv_ArbitraryFloatCosINTELILi4ELi4EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i4 signext %3, i32 2, i32 1, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Cos_A1:[0-9]+]] = OpLoad %[[Ty_4]] %[[Cos_AId:[0-9]+]] Aligned 1
+; CHECK-NEXT: %[[CosResult:[0-9]+]] = OpArbitraryFloatCosINTEL %[[Ty_4]] %[[Cos_A1]] 2 1 0 2 1
+ store i4 %4, ptr %2, align 1, !tbaa !81
+ call void @llvm.lifetime.end.p0(i64 1, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z15ap_float_sincosILi8ELi18ELi10ELi20EEvv() #3 {
+ %1 = alloca i27, align 4
+ %2 = alloca i62, align 8
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i27, ptr %1, align 4, !tbaa !83
+ %4 = call spir_func i62 @_Z33__spirv_ArbitraryFloatSinCosINTELILi27ELi31EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(i27 signext %3, i32 18, i32 20, i32 0, i32 2, i32 1) #5
+; CHECK: %[[SinCos_A1:[0-9]+]] = OpLoad %[[Ty_27]] %[[SinCos_AId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[SinCosResult:[0-9]+]] = OpArbitraryFloatSinCosINTEL %[[Ty_62]] %[[SinCos_A1]] 18 20 0 2 1
+ store i62 %4, ptr %2, align 8, !tbaa !79
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_sinpiILi3ELi6ELi6ELi6EEvv() #3 {
+ %1 = alloca i10, align 2
+ %2 = alloca i13, align 2
+ call void @llvm.lifetime.start.p0(i64 2, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ %3 = load i10, ptr %1, align 2, !tbaa !69
+ %4 = call spir_func signext i13 @_Z32__spirv_ArbitraryFloatSinPiINTELILi10ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i10 signext %3, i32 6, i32 6, i32 0, i32 2, i32 1) #5
+; CHECK: %[[SinPi_A1:[0-9]+]] = OpLoad %[[Ty_10]] %[[SinPi_AId:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[SinPiResult:[0-9]+]] = OpArbitraryFloatSinPiINTEL %[[Ty_13]] %[[SinPi_A1]] 6 6 0 2 1
+ store i13 %4, ptr %2, align 2, !tbaa !19
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_cospiILi18ELi40ELi18ELi40EEvv() #3 {
+ %1 = alloca i59, align 8
+ %2 = alloca i59, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i59, ptr %1, align 8, !tbaa !85
+ %4 = call spir_func i59 @_Z32__spirv_ArbitraryFloatCosPiINTELILi59ELi59EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i59 %3, i32 40, i32 40, i32 0, i32 2, i32 1) #5
+; CHECK: %[[CosPi_A1:[0-9]+]] = OpLoad %[[Ty_59]] %[[CosPi_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[CosPiResult:[0-9]+]] = OpArbitraryFloatCosPiINTEL %[[Ty_59]] %[[CosPi_A1]] 40 40 0 2 1
+ store i59 %4, ptr %2, align 8, !tbaa !85
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z17ap_float_sincospiILi9ELi20ELi11ELi20EEvv() #3 {
+ %1 = alloca i30, align 4
+ %2 = alloca i64, align 8
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i30, ptr %1, align 4, !tbaa !17
+ %4 = call spir_func i64 @_Z35__spirv_ArbitraryFloatSinCosPiINTELILi30ELi32EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(i30 signext %3, i32 20, i32 20, i32 0, i32 2, i32 1) #5
+; CHECK: %[[SinCosPi_A1:[0-9]+]] = OpLoad %[[Ty_30]] %[[SinCosPi_AId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[SinCosPiResult:[0-9]+]] = OpArbitraryFloatSinCosPiINTEL %[[Ty_64]] %[[SinCosPi_A1]] 20 20 0 2 1
+ store i64 %4, ptr %2, align 8, !tbaa !77
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_asinILi2ELi4ELi2ELi8EEvv() #3 {
+ %1 = alloca i7, align 1
+ %2 = alloca i11, align 2
+ call void @llvm.lifetime.start.p0(i64 1, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ %3 = load i7, ptr %1, align 1, !tbaa !43
+ %4 = call spir_func signext i11 @_Z31__spirv_ArbitraryFloatASinINTELILi7ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i7 signext %3, i32 4, i32 8, i32 0, i32 2, i32 1) #5
+; CHECK: %[[ASin_A1:[0-9]+]] = OpLoad %[[Ty_7]] %[[ASin_AId:[0-9]+]] Aligned 1
+; CHECK-NEXT: %[[ASinResult:[0-9]+]] = OpArbitraryFloatASinINTEL %[[Ty_11]] %[[ASin_A1]] 4 8 0 2 1
+ store i11 %4, ptr %2, align 2, !tbaa !27
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z15ap_float_asinpiILi11ELi23ELi11ELi23EEvv() #3 {
+ %1 = alloca i35, align 8
+ %2 = alloca i35, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i35, ptr %1, align 8, !tbaa !87
+ %4 = call spir_func i35 @_Z33__spirv_ArbitraryFloatASinPiINTELILi35ELi35EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i35 %3, i32 23, i32 23, i32 0, i32 2, i32 1) #5
+; CHECK: %[[ASinPi_A1:[0-9]+]] = OpLoad %[[Ty_35]] %[[ASinPi_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[ASinPiResult:[0-9]+]] = OpArbitraryFloatASinPiINTEL %[[Ty_35]] %[[ASinPi_A1]] 23 23 0 2 1
+ store i35 %4, ptr %2, align 8, !tbaa !87
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_acosILi4ELi9ELi3ELi10EEvv() #3 {
+ %1 = alloca i14, align 2
+ %2 = alloca i14, align 2
+ call void @llvm.lifetime.start.p0(i64 2, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ %3 = load i14, ptr %1, align 2, !tbaa !23
+ %4 = call spir_func signext i14 @_Z31__spirv_ArbitraryFloatACosINTELILi14ELi14EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i14 signext %3, i32 9, i32 10, i32 0, i32 2, i32 1) #5
+; CHECK: %[[ACos_A1:[0-9]+]] = OpLoad %[[Ty_14]] %[[ACos_AId:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[ACosResult:[0-9]+]] = OpArbitraryFloatACosINTEL %[[Ty_14]] %[[ACos_A1]] 9 10 0 2 1
+ store i14 %4, ptr %2, align 2, !tbaa !23
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z15ap_float_acospiILi2ELi5ELi3ELi4EEvv() #3 {
+ %1 = alloca i8, align 1
+ %2 = alloca i8, align 1
+ call void @llvm.lifetime.start.p0(i64 1, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %2) #5
+ %3 = load i8, ptr %1, align 1, !tbaa !67
+ %4 = call spir_func signext i8 @_Z33__spirv_ArbitraryFloatACosPiINTELILi8ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i8 signext %3, i32 5, i32 4, i32 0, i32 2, i32 1) #5
+; CHECK: %[[ACosPi_A1:[0-9]+]] = OpLoad %[[Ty_8]] %[[ACosPi_AId:[0-9]+]] Aligned 1
+; CHECK-NEXT: %[[ACosPiResult:[0-9]+]] = OpArbitraryFloatACosPiINTEL %[[Ty_8]] %[[ACosPi_A1]] 5 4 0 2 1
+ store i8 %4, ptr %2, align 1, !tbaa !67
+ call void @llvm.lifetime.end.p0(i64 1, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_atanILi12ELi31ELi12ELi31EEvv() #3 {
+ %1 = alloca i44, align 8
+ %2 = alloca i44, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i44, ptr %1, align 8, !tbaa !89
+ %4 = call spir_func i44 @_Z31__spirv_ArbitraryFloatATanINTELILi44ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i44 %3, i32 31, i32 31, i32 0, i32 2, i32 1) #5
+; CHECK: %[[ATan_A1:[0-9]+]] = OpLoad %[[Ty_44]] %[[ATan_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[ATanResult:[0-9]+]] = OpArbitraryFloatATanINTEL %[[Ty_44]] %[[ATan_A1]] 31 31 0 2 1
+ store i44 %4, ptr %2, align 8, !tbaa !89
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z15ap_float_atanpiILi1ELi38ELi1ELi32EEvv() #3 {
+ %1 = alloca i40, align 8
+ %2 = alloca i34, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ %3 = load i40, ptr %1, align 8, !tbaa !9
+ %4 = call spir_func i34 @_Z33__spirv_ArbitraryFloatATanPiINTELILi40ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i40 %3, i32 38, i32 32, i32 0, i32 2, i32 1) #5
+; CHECK: %[[ATanPi_A1:[0-9]+]] = OpLoad %[[Ty_40]] %[[ATanPi_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[ATanPiResult:[0-9]+]] = OpArbitraryFloatATanPiINTEL %[[Ty_34]] %[[ATanPi_A1]] 38 32 0 2 1
+ store i34 %4, ptr %2, align 8, !tbaa !53
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_atan2ILi7ELi16ELi7ELi17ELi8ELi18EEvv() #3 {
+ %1 = alloca i24, align 4
+ %2 = alloca i25, align 4
+ %3 = alloca i27, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
+ %4 = load i24, ptr %1, align 4, !tbaa !91
+ %5 = load i25, ptr %2, align 4, !tbaa !13
+ %6 = call spir_func signext i27 @_Z32__spirv_ArbitraryFloatATan2INTELILi24ELi25ELi27EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i24 signext %4, i32 16, i25 signext %5, i32 17, i32 18, i32 0, i32 2, i32 1) #5
+; CHECK: %[[ATan2_A1:[0-9]+]] = OpLoad %[[Ty_24]] %[[ATan2_AId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[ATan2_B1:[0-9]+]] = OpLoad %[[Ty_25]] %[[ATan2_BId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[ATan2Result:[0-9]+]] = OpArbitraryFloatATan2INTEL %[[Ty_27]] %[[ATan2_A1]] 16 %[[ATan2_B1]] 17 18 0 2 1
+ store i27 %6, ptr %3, align 4, !tbaa !83
+ call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z12ap_float_powILi8ELi8ELi9ELi9ELi10ELi10EEvv() #3 {
+ %1 = alloca i17, align 4
+ %2 = alloca i19, align 4
+ %3 = alloca i21, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
+ %4 = load i17, ptr %1, align 4, !tbaa !61
+ %5 = load i19, ptr %2, align 4, !tbaa !93
+ %6 = call spir_func signext i21 @_Z30__spirv_ArbitraryFloatPowINTELILi17ELi19ELi21EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i17 signext %4, i32 8, i19 signext %5, i32 9, i32 10, i32 0, i32 2, i32 1) #5
+; CHECK: %[[Pow_A1:[0-9]+]] = OpLoad %[[Ty_17]] %[[Pow_AId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[Pow_B1:[0-9]+]] = OpLoad %[[Ty_19]] %[[Pow_BId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[PowResult:[0-9]+]] = OpArbitraryFloatPowINTEL %[[Ty_21]] %[[Pow_A1]] 8 %[[Pow_B1]] 9 10 0 2 1
+ store i21 %6, ptr %3, align 4, !tbaa !95
+ call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_powrILi18ELi35ELi19ELi35ELi20ELi35EEvv() #3 {
+ %1 = alloca i54, align 8
+ %2 = alloca i55, align 8
+ %3 = alloca i56, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %3) #5
+ %4 = load i54, ptr %1, align 8, !tbaa !97
+ %5 = load i55, ptr %2, align 8, !tbaa !45
+ %6 = call spir_func i56 @_Z31__spirv_ArbitraryFloatPowRINTELILi54ELi55ELi56EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i54 %4, i32 35, i55 %5, i32 35, i32 35, i32 0, i32 2, i32 1) #5
+; CHECK: %[[PowR_A1:[0-9]+]] = OpLoad %[[Ty_54]] %[[PowR_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[PowR_B1:[0-9]+]] = OpLoad %[[Ty_55]] %[[PowR_BId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[PowRResult:[0-9]+]] = OpArbitraryFloatPowRINTEL %[[Ty_56]] %[[PowR_A1]] 35 %[[PowR_B1]] 35 35 0 2 1
+ store i56 %6, ptr %3, align 8, !tbaa !99
+ call void @llvm.lifetime.end.p0(i64 8, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_pownILi4ELi7ELi10ELi5ELi9EEvv() #3 {
+ %1 = alloca i12, align 2
+ %2 = alloca i10, align 2
+ %3 = alloca i15, align 2
+ call void @llvm.lifetime.start.p0(i64 2, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %3) #5
+ %4 = load i12, ptr %1, align 2, !tbaa !101
+ %5 = load i10, ptr %2, align 2, !tbaa !69
+ %6 = call spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi12ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(i12 signext %4, i32 7, i10 signext %5, i1 zeroext false, i32 9, i32 0, i32 2, i32 1) #5
+; CHECK: %[[PowN_A1:[0-9]+]] = OpLoad %[[Ty_12]] %[[PowN_AId:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[PowN_B1:[0-9]+]] = OpLoad %[[Ty_10]] %[[PowN_BId:[0-9]+]] Aligned 2
+; CHECK-NEXT: %[[PowNResult:[0-9]+]] = OpArbitraryFloatPowNINTEL %[[Ty_15]] %[[PowN_A1]] 7 %[[PowN_B1]] 0 9 0 2 1
+ store i15 %6, ptr %3, align 2, !tbaa !21
+ call void @llvm.lifetime.end.p0(i64 2, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z15ap_float_sincosILi8ELi18ELi10ELi20EEvv_() #3 {
+ %1 = alloca i34, align 8
+ %2 = addrspacecast ptr %1 to ptr addrspace(4)
+ %3 = alloca i64, align 8
+ %4 = addrspacecast ptr %3 to ptr addrspace(4)
+ call void @llvm.lifetime.start.p0(i64 8, ptr %1)
+ call void @llvm.lifetime.start.p0(i64 16, ptr %3)
+ %5 = load i34, ptr addrspace(4) %2, align 8
+ call spir_func void @_Z33__spirv_ArbitraryFloatSinCosINTELILi34ELi64EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(ptr addrspace(4) sret(i64) align 8 %4, i34 %5, i32 18, i32 20, i32 0, i32 2, i32 1) #5
+; CHECK: %[[SinCos_A1:[0-9]+]] = OpLoad %[[Ty_34]] %[[SinCos_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[SinCosResult:[0-9]+]] = OpArbitraryFloatSinCosINTEL %[[Ty_64]] %[[SinCos_A1]] 18 20 0 2 1
+; CHECK-NEXT: OpStore %[[#]] %[[SinCosResult]] Aligned 4
+ %6 = load i64, ptr addrspace(4) %4, align 8
+ store i64 %6, ptr addrspace(4) %4, align 8
+ call void @llvm.lifetime.end.p0(i64 8, ptr %1)
+ call void @llvm.lifetime.end.p0(i64 16, ptr %3)
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z14ap_float_atan2ILi7ELi16ELi7ELi17ELi8ELi18EEvv_() #3 {
+ %1 = alloca i24, align 4
+ %2 = alloca i25, align 4
+ %3 = alloca i64, align 8
+ %4 = addrspacecast ptr %3 to ptr addrspace(4)
+ call void @llvm.lifetime.start.p0(i64 4, ptr %1) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.start.p0(i64 16, ptr %3) #5
+ %5 = load i24, ptr %1, align 4, !tbaa !91
+ %6 = load i25, ptr %2, align 4, !tbaa !13
+ call spir_func void @_Z32__spirv_ArbitraryFloatATan2INTELILi24ELi25ELi64EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(ptr addrspace(4) sret(i64) align 8 %4, i24 signext %5, i32 16, i25 signext %6, i32 17, i32 18, i32 0, i32 2, i32 1) #5
+; CHECK: %[[ATan2_A1:[0-9]+]] = OpLoad %[[Ty_24]] %[[ATan2_AId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[ATan2_B1:[0-9]+]] = OpLoad %[[Ty_25]] %[[ATan2_BId:[0-9]+]] Aligned 4
+; CHECK-NEXT: %[[ATan2Result:[0-9]+]] = OpArbitraryFloatATan2INTEL %[[Ty_64]] %[[ATan2_A1]] 16 %[[ATan2_B1]] 17 18 0 2 1
+; CHECK-NEXT: OpStore %[[#]] %[[ATan2Result]]
+ %7 = load i64, ptr addrspace(4) %4, align 8
+ store i64 %7, ptr addrspace(4) %4, align 8
+ call void @llvm.lifetime.end.p0(i64 16, ptr %3) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %1) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_pownILi64ELi7ELi10ELi5ELi9EEvv() #3 {
+entry:
+ %A = alloca i64, align 8
+ %A.ascast = addrspacecast ptr %A to ptr addrspace(4)
+ %B = alloca i10, align 2
+ %B.ascast = addrspacecast ptr %B to ptr addrspace(4)
+ %pown_res = alloca i15, align 2
+ %pown_res.ascast = addrspacecast ptr %pown_res to ptr addrspace(4)
+ %indirect-arg-temp = alloca i64, align 8
+ call void @llvm.lifetime.start.p0(i64 16, ptr %A) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %B) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %pown_res) #5
+ %0 = load i64, ptr addrspace(4) %A.ascast, align 8
+ %1 = load i10, ptr addrspace(4) %B.ascast, align 2
+ store i64 %0, ptr %indirect-arg-temp, align 8
+; CHECK: %[[#]] = OpLoad %[[Ty_64]] %[[#]] Aligned 8
+; CHECK: %[[PowN_A1:[0-9]+]] = OpLoad %[[Ty_64]] %[[PowN_AId:[0-9]+]] Aligned 8
+; CHECK-NEXT: %[[PowN_B1:[0-9]+]] = OpLoad %[[Ty_10]] %[[PowN_BId:[0-9]+]] Aligned 2
+; CHECK-NEXT: OpStore %[[PtrId:[0-9]+]] %[[PowN_A1]] Aligned 8
+; CHECK-NEXT: %[[PowNResult:[0-9]+]] = OpArbitraryFloatPowNINTEL %[[Ty_15]] %[[#]] 7 %[[PowN_B1]] 1 9 0 2 1
+; CHECK-NEXT: OpStore %[[PtrId:[0-9]+]] %[[PowNResult]] Aligned 2
+ %call = call spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi64ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(ptr byval(i64) align 8 %indirect-arg-temp, i32 7, i10 signext %1, i1 zeroext true, i32 9, i32 0, i32 2, i32 1) #4
+ store i15 %call, ptr addrspace(4) %pown_res.ascast, align 2
+ call void @llvm.lifetime.end.p0(i64 2, ptr %pown_res) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %B) #5
+ call void @llvm.lifetime.end.p0(i64 16, ptr %A) #5
+ ret void
+}
+; Function Attrs: nounwind
+declare dso_local spir_func i40 @_Z31__spirv_ArbitraryFloatCastINTELILi40ELi40EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i40, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i25 @_Z38__spirv_ArbitraryFloatCastFromIntINTELILi43ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i43, i32, i1 zeroext, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i30 @_Z36__spirv_ArbitraryFloatCastToIntINTELILi23ELi30EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i23 signext, i32, i1 zeroext, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i14 @_Z30__spirv_ArbitraryFloatAddINTELILi13ELi15ELi14EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i13 signext, i32, i15 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i13 @_Z30__spirv_ArbitraryFloatAddINTELILi15ELi14ELi13EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i15 signext, i32, i14 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i13 @_Z30__spirv_ArbitraryFloatSubINTELILi9ELi11ELi13EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i9 signext, i32, i11 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i51 @_Z30__spirv_ArbitraryFloatMulINTELILi51ELi51ELi51EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i51, i32, i51, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i18 @_Z30__spirv_ArbitraryFloatDivINTELILi16ELi16ELi18EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i16 signext, i32, i16 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatGTINTELILi63ELi63EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i63, i32, i63, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatGEINTELILi47ELi47EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i47, i32, i47, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatLTINTELILi5ELi7EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i5 signext, i32, i7 signext, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatLEINTELILi55ELi55EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i55, i32, i55, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatEQINTELILi20ELi15EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i20 signext, i32, i15 signext, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i39 @_Z32__spirv_ArbitraryFloatRecipINTELILi39ELi39EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i39, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i34 @_Z32__spirv_ArbitraryFloatRSqrtINTELILi32ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i32, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i2 @_Z31__spirv_ArbitraryFloatCbrtINTELILi2ELi2EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i2 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i42 @_Z32__spirv_ArbitraryFloatHypotINTELILi41ELi43ELi42EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i41, i32, i43, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i17 @_Z31__spirv_ArbitraryFloatSqrtINTELILi15ELi17EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i15 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i50 @_Z30__spirv_ArbitraryFloatLogINTELILi50ELi50EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i50, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i38 @_Z31__spirv_ArbitraryFloatLog2INTELILi38ELi38EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i38, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i10 @_Z32__spirv_ArbitraryFloatLog10INTELILi8ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i8 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i49 @_Z32__spirv_ArbitraryFloatLog1pINTELILi48ELi49EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i48, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i42 @_Z30__spirv_ArbitraryFloatExpINTELILi42ELi42EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i42, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i5 @_Z31__spirv_ArbitraryFloatExp2INTELILi3ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i3 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i25 @_Z32__spirv_ArbitraryFloatExp10INTELILi25ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i25 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i62 @_Z32__spirv_ArbitraryFloatExpm1INTELILi64ELi62EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i64, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i34 @_Z30__spirv_ArbitraryFloatSinINTELILi30ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i30 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i4 @_Z30__spirv_ArbitraryFloatCosINTELILi4ELi4EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i4 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i62 @_Z33__spirv_ArbitraryFloatSinCosINTELILi27ELi31EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(i27 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i13 @_Z32__spirv_ArbitraryFloatSinPiINTELILi10ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i10 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i59 @_Z32__spirv_ArbitraryFloatCosPiINTELILi59ELi59EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i59, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i64 @_Z35__spirv_ArbitraryFloatSinCosPiINTELILi30ELi32EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(i30 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i11 @_Z31__spirv_ArbitraryFloatASinINTELILi7ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i7 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i35 @_Z33__spirv_ArbitraryFloatASinPiINTELILi35ELi35EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i35, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i14 @_Z31__spirv_ArbitraryFloatACosINTELILi14ELi14EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i14 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i8 @_Z33__spirv_ArbitraryFloatACosPiINTELILi8ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i8 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i44 @_Z31__spirv_ArbitraryFloatATanINTELILi44ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i44, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i34 @_Z33__spirv_ArbitraryFloatATanPiINTELILi40ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i40, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i27 @_Z32__spirv_ArbitraryFloatATan2INTELILi24ELi25ELi27EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i24 signext, i32, i25 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i21 @_Z30__spirv_ArbitraryFloatPowINTELILi17ELi19ELi21EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i17 signext, i32, i19 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i56 @_Z31__spirv_ArbitraryFloatPowRINTELILi54ELi55ELi56EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i54, i32, i55, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi12ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(i12 signext, i32, i10 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func void @_Z33__spirv_ArbitraryFloatSinCosINTELILi34ELi64EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(ptr addrspace(4) sret(i64) align 8, i34, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func void @_Z32__spirv_ArbitraryFloatATan2INTELILi24ELi25ELi64EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(ptr addrspace(4) sret(i64) align 8, i24 signext, i32, i25 signext, i32, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi64ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(ptr byval(i64) align 8, i32, i10 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+attributes #0 = { norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { argmemonly nounwind willreturn }
+attributes #2 = { inlinehint norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.spir.version = !{!1}
+!spirv.Source = !{!2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{i32 4, i32 100000}
+!3 = !{!"clang version 11.0.0"}
+!4 = !{}
+!5 = !{!6, !6, i64 0}
+!6 = !{!"any pointer", !7, i64 0}
+!7 = !{!"omnipotent char", !8, i64 0}
+!8 = !{!"Simple C++ TBAA"}
+!9 = !{!10, !10, i64 0}
+!10 = !{!"_ExtInt(40)", !7, i64 0}
+!11 = !{!12, !12, i64 0}
+!12 = !{!"_ExtInt(43)", !7, i64 0}
+!13 = !{!14, !14, i64 0}
+!14 = !{!"_ExtInt(25)", !7, i64 0}
+!15 = !{!16, !16, i64 0}
+!16 = !{!"_ExtInt(23)", !7, i64 0}
+!17 = !{!18, !18, i64 0}
+!18 = !{!"_ExtInt(30)", !7, i64 0}
+!19 = !{!20, !20, i64 0}
+!20 = !{!"_ExtInt(13)", !7, i64 0}
+!21 = !{!22, !22, i64 0}
+!22 = !{!"_ExtInt(15)", !7, i64 0}
+!23 = !{!24, !24, i64 0}
+!24 = !{!"_ExtInt(14)", !7, i64 0}
+!25 = !{!26, !26, i64 0}
+!26 = !{!"_ExtInt(9)", !7, i64 0}
+!27 = !{!28, !28, i64 0}
+!28 = !{!"_ExtInt(11)", !7, i64 0}
+!29 = !{!30, !30, i64 0}
+!30 = !{!"_ExtInt(51)", !7, i64 0}
+!31 = !{!32, !32, i64 0}
+!32 = !{!"_ExtInt(16)", !7, i64 0}
+!33 = !{!34, !34, i64 0}
+!34 = !{!"_ExtInt(18)", !7, i64 0}
+!35 = !{!36, !36, i64 0}
+!36 = !{!"_ExtInt(63)", !7, i64 0}
+!37 = !{!38, !38, i64 0}
+!38 = !{!"bool", !7, i64 0}
+!39 = !{!40, !40, i64 0}
+!40 = !{!"_ExtInt(47)", !7, i64 0}
+!41 = !{!42, !42, i64 0}
+!42 = !{!"_ExtInt(5)", !7, i64 0}
+!43 = !{!44, !44, i64 0}
+!44 = !{!"_ExtInt(7)", !7, i64 0}
+!45 = !{!46, !46, i64 0}
+!46 = !{!"_ExtInt(55)", !7, i64 0}
+!47 = !{!48, !48, i64 0}
+!48 = !{!"_ExtInt(20)", !7, i64 0}
+!49 = !{!50, !50, i64 0}
+!50 = !{!"_ExtInt(39)", !7, i64 0}
+!51 = !{!52, !52, i64 0}
+!52 = !{!"_ExtInt(32)", !7, i64 0}
+!53 = !{!54, !54, i64 0}
+!54 = !{!"_ExtInt(34)", !7, i64 0}
+!55 = !{!56, !56, i64 0}
+!56 = !{!"_ExtInt(2)", !7, i64 0}
+!57 = !{!58, !58, i64 0}
+!58 = !{!"_ExtInt(41)", !7, i64 0}
+!59 = !{!60, !60, i64 0}
+!60 = !{!"_ExtInt(42)", !7, i64 0}
+!61 = !{!62, !62, i64 0}
+!62 = !{!"_ExtInt(17)", !7, i64 0}
+!63 = !{!64, !64, i64 0}
+!64 = !{!"_ExtInt(50)", !7, i64 0}
+!65 = !{!66, !66, i64 0}
+!66 = !{!"_ExtInt(38)", !7, i64 0}
+!67 = !{!68, !68, i64 0}
+!68 = !{!"_ExtInt(8)", !7, i64 0}
+!69 = !{!70, !70, i64 0}
+!70 = !{!"_ExtInt(10)", !7, i64 0}
+!71 = !{!72, !72, i64 0}
+!72 = !{!"_ExtInt(48)", !7, i64 0}
+!73 = !{!74, !74, i64 0}
+!74 = !{!"_ExtInt(49)", !7, i64 0}
+!75 = !{!76, !76, i64 0}
+!76 = !{!"_ExtInt(3)", !7, i64 0}
+!77 = !{!78, !78, i64 0}
+!78 = !{!"_ExtInt(64)", !7, i64 0}
+!79 = !{!80, !80, i64 0}
+!80 = !{!"_ExtInt(62)", !7, i64 0}
+!81 = !{!82, !82, i64 0}
+!82 = !{!"_ExtInt(4)", !7, i64 0}
+!83 = !{!84, !84, i64 0}
+!84 = !{!"_ExtInt(27)", !7, i64 0}
+!85 = !{!86, !86, i64 0}
+!86 = !{!"_ExtInt(59)", !7, i64 0}
+!87 = !{!88, !88, i64 0}
+!88 = !{!"_ExtInt(35)", !7, i64 0}
+!89 = !{!90, !90, i64 0}
+!90 = !{!"_ExtInt(44)", !7, i64 0}
+!91 = !{!92, !92, i64 0}
+!92 = !{!"_ExtInt(24)", !7, i64 0}
+!93 = !{!94, !94, i64 0}
+!94 = !{!"_ExtInt(19)", !7, i64 0}
+!95 = !{!96, !96, i64 0}
+!96 = !{!"_ExtInt(21)", !7, i64 0}
+!97 = !{!98, !98, i64 0}
+!98 = !{!"_ExtInt(54)", !7, i64 0}
+!99 = !{!100, !100, i64 0}
+!100 = !{!"_ExtInt(56)", !7, i64 0}
+!101 = !{!102, !102, i64 0}
+!102 = !{!"_ExtInt(12)", !7, i64 0}
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