[llvm] [GlobalISel] Add computeNumSignBits for G_SHUFFLE_VECTOR (PR #139505)

[Matt Arsenault via llvm-commits]

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@@ -836,6 +837,28 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
       return TyBits - 1; // Every always-zero bit is a sign bit.
     break;
   }
+  case TargetOpcode::G_SHUFFLE_VECTOR: {
+    // Collect the minimum number of sign bits that are shared by every vector
+    // element referenced by the shuffle.
+    APInt DemandedLHS, DemandedRHS;
+    unsigned NumElts = MRI.getType(MI.getOperand(1).getReg()).getNumElements();
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arsenm wrote:

Use temp register for MI.getOperand(1).getReg() and avoid the line break below 

https://github.com/llvm/llvm-project/pull/139505