[llvm] bf70f84 - [RISCV][Docs] Correct links to Xmipscmov and Xmipslsp specifications. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-05-12T16:57:41-07:00
New Revision: bf70f84e173fac1b220cebb4f503d0ab752d6a9f

URL: https://github.com/llvm/llvm-project/commit/bf70f84e173fac1b220cebb4f503d0ab752d6a9f
DIFF: https://github.com/llvm/llvm-project/commit/bf70f84e173fac1b220cebb4f503d0ab752d6a9f.diff

LOG: [RISCV][Docs] Correct links to Xmipscmov and Xmipslsp specifications. NFC

Need to add 2 underscores after the URL.

Added: 
    

Modified: 
    llvm/docs/RISCVUsage.rst

Removed: 
    


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diff  --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 63e594152992e..0e0567cb7c7e6 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -494,10 +494,10 @@ The current vendor extensions supported are:
   LLVM implements `version 0.2 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm.  All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
 
 ``Xmipscmov``
-  LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS.
+  LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.
 
 ``Xmipslsp``
-  LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS.
+  LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.
 
 ``experimental-XRivosVisni``
   LLVM implements `version 0.1 of the Rivos Vector Integer Small New Instructions extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.