[llvm] [DAGCombiner] Fold pattern for srl-shl-zext (PR #138290)

[Simon Pilgrim via llvm-commits]

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@@ -10972,6 +10972,24 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
       return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1);
   }
 
+  // fold (srl (logic_op x, (shl (zext y), c1)), c1)
+  //   -> (logic_op (srl x, c1), (zext y))
+  // c1 <= leadingzeros(zext(y))
+  SDValue X, ZExtY;
+  if (N1C && sd_match(N0, m_OneUse(m_BitwiseLogic(
+                              m_Value(X),
+                              m_OneUse(m_Shl(m_AllOf(m_Value(ZExtY),
+                                                     m_Opc(ISD::ZERO_EXTEND)),
+                                             m_Specific(N1))))))) {
+    unsigned NumLeadingZeros =
+        ZExtY.getValueType().getScalarSizeInBits() -
+        ZExtY.getOperand(0).getValueType().getScalarSizeInBits();
+    if (N1C->getZExtValue() <= NumLeadingZeros) {
+      return DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
+                         DAG.getNode(ISD::SRL, SDLoc(N0), VT, X, N1), ZExtY);
+    }
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RKSimon wrote:

the coding style just refers to "simple statements" :) 

https://github.com/llvm/llvm-project/pull/138290