[llvm] [PowerPC] catch v2i64 shift left by 1 is add case (PR #138772)

[Amy Kwan via llvm-commits]

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@@ -18456,10 +18456,45 @@ static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N,
   return SDValue();
 }
 
+SDValue PPCTargetLowering::combineVectorSHL(SDNode *N,
+                                            DAGCombinerInfo &DCI) const {
+  assert(N->getValueType(0).isVector() && "Vector type expected.");
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amy-kwan wrote:

Minor nit, but we can probably pull out `N->getValueType(0)` and `N->getOperand(0)` in this function since we use them few times.

https://github.com/llvm/llvm-project/pull/138772