[llvm] [AMDGPU] si-peephole-sdwa: Fix cndmask vcc use for wave32 (PR #139541)

[Frederik Harwath via llvm-commits]

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@@ -0,0 +1,40 @@
+; RUN: llc %s -march=amdgcn -mcpu=gfx1030 -o - 2>&1 | FileCheck %s
+
+; In this test, V_CNDMASK_B32_e64 gets converted to V_CNDMASK_B32_e32,
+; but the expected conversion to SDWA does not occur.  This led to a
+; compilation error, because the use of $vcc in the resulting
+; instruction must be fixed to $vcc_lo for wave32 which only happened
+; after the full conversion to SDWA.
+
+
+; CHECK-NOT: {{.*}}V_CNDMASK_B32_e32{{.*}}$vcc
+; CHECK-NOT: {{.*}}Bad machine code: Virtual register defs don't dominate all uses
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frederik-h wrote:

I think I cannot add it to the existing test file for "wave32" which uses "--run-pass=si-peephole-sdwa". The mir parser cannot read the mir that llc outputs with "--stop-before=si-peephole-sdwa" because it contains instructions with implicit "vcc_lo" operands. The parser insists on those being "vcc" instead because it does not take the wave32/wave64 distinction into account while checking the correctness of the implicit operands.

https://github.com/llvm/llvm-project/pull/139541