[llvm] [GISel][AArch64] Added more efficient lowering of Bitreverse (PR #139233)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon May 12 04:27:39 PDT 2025
================
@@ -8985,49 +8985,62 @@ static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
auto [Dst, Src] = MI.getFirst2Regs();
- const LLT Ty = MRI.getType(Src);
- unsigned Size = Ty.getScalarSizeInBits();
+ const LLT SrcTy = MRI.getType(Src);
+ unsigned Size = SrcTy.getScalarSizeInBits();
+ unsigned VSize = SrcTy.getSizeInBits();
if (Size >= 8) {
- MachineInstrBuilder BSWAP =
- MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src});
-
- // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
- // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
- // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
- MachineInstrBuilder Swap4 =
- SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0)));
-
- // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
- // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
- // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
- MachineInstrBuilder Swap2 =
- SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC)));
-
- // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5
- // 6|7
- // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
- // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
- SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA)));
+ LLT VTy = LLT::fixed_vector(VSize / 8, 8);
+
+ if (LI.isLegal({TargetOpcode::G_BITREVERSE, {VTy, VTy}})) {
----------------
davemgreen wrote:
Is it worth checking that `[Elt]Size % 8 == 0` too?
https://github.com/llvm/llvm-project/pull/139233
More information about the llvm-commits
mailing list