[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Kiva (imkiva)

<details>
<summary>Changes</summary>

This PR adds the missing intrinsic `__builtin_riscv_pause` for the zihintpause extension.

Spec: https://five-embeddev.com/riscv-user-isa-manual/Priv-v1.12/zihintpause.html
Fixes #<!-- -->129961 

---
Full diff: https://github.com/llvm/llvm-project/pull/139519.diff


7 Files Affected:

- (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+7) 
- (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+6) 
- (added) clang/test/CodeGen/RISCV/riscv-zihintpause.c (+14) 
- (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+6) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+3) 
- (added) llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td (+10) 
- (added) llvm/test/CodeGen/RISCV/riscv-zihintpause.ll (+14) 


``````````diff
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 3263603a8a1cf..598ec2abeeae1 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
 
+//===----------------------------------------------------------------------===//
+// Zihintpause extension.
+//===----------------------------------------------------------------------===//
+let Features = "zihintpause" in {
+def pause : RISCVBuiltin<"void(...)">;
+} // Features = "zihintntl"
+
 //===----------------------------------------------------------------------===//
 // XCV extensions.
 //===----------------------------------------------------------------------===//
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index 3335239b0b6c2..0cd4f3c935e92 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -357,6 +357,12 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
 
     return Store;
   }
+  // Zihintpause
+  case RISCV::BI__builtin_riscv_pause: {
+    llvm::Function *Fn = CGM.getIntrinsic(llvm::Intrinsic::riscv_pause);
+    return Builder.CreateCall(Fn, {});
+  }
+
   // XCValu
   case RISCV::BI__builtin_riscv_cv_alu_addN:
     ID = Intrinsic::riscv_cv_alu_addN;
diff --git a/clang/test/CodeGen/RISCV/riscv-zihintpause.c b/clang/test/CodeGen/RISCV/riscv-zihintpause.c
new file mode 100644
index 0000000000000..76d2f289a075b
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-zihintpause.c
@@ -0,0 +1,14 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+
+#include <stdint.h>
+
+// CHECK-LABEL: @test_builtin_pause(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    call void @llvm.riscv.pause()
+// CHECK-NEXT:    ret void
+//
+void test_builtin_pause() {
+    __builtin_riscv_pause();
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 18b2883eb00e7..782c583db89de 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1886,6 +1886,12 @@ let TargetPrefix = "riscv" in {
   def int_riscv_vsm3me   : RISCVBinaryAAXUnMasked;
 } // TargetPrefix = "riscv"
 
+// Zihintpause extensions
+//===----------------------------------------------------------------------===//
+let TargetPrefix = "riscv" in {
+  def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+} // TargetPrefix = "riscv"
+
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 include "llvm/IR/IntrinsicsRISCVXTHead.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index e9bdeb88e4ca8..8a5b52e591433 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2242,6 +2242,9 @@ include "RISCVInstrInfoZclsd.td"
 // Short Forward Branch
 include "RISCVInstrInfoSFB.td"
 
+// Zihintpause extensions
+include "RISCVInstrInfoZihintpause.td"
+
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td
new file mode 100644
index 0000000000000..60bfdf96c3f98
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td
@@ -0,0 +1,10 @@
+//===-- RISCVInstrInfoZihintpause.td -----------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+
+let Predicates = [HasStdExtZihintpause] in {
+  def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>;
+}
diff --git a/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
new file mode 100644
index 0000000000000..6c6f5e20a8b48
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RVPAUSE
+
+declare void @llvm.riscv.pause()
+
+define void @test_pause() {
+; RVPAUSE-LABEL: test_pause:
+; RVPAUSE:       # %bb.0:
+; RVPAUSE-NEXT:    pause
+; RVPAUSE-NEXT:    ret
+  call void @llvm.riscv.pause()
+  ret void
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/139519