[llvm] [AArch64][SVE] Add lowering for PARTIAL_REDUCE_U/SMLA to USDOT (PR #131327)

[Sander de Smalen via llvm-commits]

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@@ -1869,7 +1869,20 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
     setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
 
+    // 8to64
     setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv16i8, Custom);
+
+    if (Subtarget->hasMatMulInt8()) {
+      // USDOT
+      setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i64, Custom);
+      setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i32, Custom);
+      setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv4i64, Custom);
+      setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv8i32, Custom);
+      setPartialReduceMLAAction(MVT::nxv8i16, MVT::nxv16i16, Custom);
+      setPartialReduceMLAAction(MVT::nxv16i8, MVT::nxv32i8, Custom);
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sdesmalen-arm wrote:

I'd expect the cases you've handled above (where all types are legal) to be sufficient. Why did you have to add this?

https://github.com/llvm/llvm-project/pull/131327