[llvm] [NVPTX] Vectorize and lower 256-bit global loads/stores for sm_100+/ptx88+ (PR #139292)

[Alex MacLean via llvm-commits]

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@@ -3201,7 +3229,12 @@ NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
   if (ValVT != MemVT)
     return SDValue();
 
-  const auto NumEltsAndEltVT = getVectorLoweringShape(ValVT);
+  // 256-bit vectors are only allowed iff the address is global
+  // and the target supports 256-bit loads/stores
+  unsigned AddrSpace = cast<MemSDNode>(N)->getAddressSpace();
+  bool CanLowerTo256Bit =
+      AddrSpace == ADDRESS_SPACE_GLOBAL && STI.has256BitMaskedLoadStore();
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AlexMaclean wrote:

This logic appears in several different places. Maybe it would be good to extract into a one-line function so that if the AddrSpace restrictions ever change we don't need to change many different places. 

https://github.com/llvm/llvm-project/pull/139292