[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)

[Sam Elliott via llvm-commits]

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@@ -23,15 +23,15 @@ def SDT_StorePair : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
                                          SDTCisPtrTy<2>,
                                          SDTCisVT<3, XLenVT>]>;
 
-def th_lwud : SDNode<"RISCVISD::TH_LWUD", SDT_LoadPair,
+def th_lwud : RVSDNode<"TH_LWUD", SDT_LoadPair,
                      [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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lenary wrote:

Done (and the lines below)

https://github.com/llvm/llvm-project/pull/138381