[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)

Sam Elliott via llvm-commits llvm-commits at lists.llvm.org
Thu May 8 11:47:47 PDT 2025


================
@@ -11,15 +11,48 @@
 
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 
+#define GET_SDNODE_ENUM
+#include "RISCVGenSDNodeInfo.inc"
+
 namespace llvm {
 
-class RISCVSelectionDAGInfo : public SelectionDAGTargetInfo {
+namespace RISCVISD {
+// RISCVISD Node TSFlags
+enum : unsigned {
----------------
lenary wrote:

One better: introduced a `using` for this in a target-independent header, so that if tsflags is extended it only needs to be updated in one place... hopefully.

https://github.com/llvm/llvm-project/pull/138381


More information about the llvm-commits mailing list