[llvm] 21130d3 - [RISCV] One last migration to getInsertSubvector [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2025-05-08T11:26:42-07:00
New Revision: 21130d3f068ae5d9f3d11750f5a3bcf63ed36082

URL: https://github.com/llvm/llvm-project/commit/21130d3f068ae5d9f3d11750f5a3bcf63ed36082
DIFF: https://github.com/llvm/llvm-project/commit/21130d3f068ae5d9f3d11750f5a3bcf63ed36082.diff

LOG: [RISCV] One last migration to getInsertSubvector [nfc]

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 63245e29a67a8..d65e921dfc660 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11973,9 +11973,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
       // Reassemble the low and high pieces reversed.
       // FIXME: This is a CONCAT_VECTORS.
       SDValue Res = DAG.getInsertSubvector(DL, DAG.getUNDEF(VecVT), Hi, 0);
-      return DAG.getNode(
-          ISD::INSERT_SUBVECTOR, DL, VecVT, Res, Lo,
-          DAG.getVectorIdxConstant(LoVT.getVectorMinNumElements(), DL));
+      return DAG.getInsertSubvector(DL, Res, Lo,
+                                    LoVT.getVectorMinNumElements());
     }
 
     // Just promote the int type to i16 which will double the LMUL.