[llvm] [WIP][AMDGPU][MC] Support 128b rsrc reg in mimg instructions (PR #139121)

[Jun Wang via llvm-commits]

jwanggit86 wrote:

This is an alternative solution to the problem addressed by [PR 132264](https://github.com/llvm/llvm-project/pull/132264). One concern with PR 132264 is that the number of MIMG instructions is nearly doubled ( from ~14000 to 2x). In this solution, a new register class SReg_RSRC is created that contains both 256b and 128b SRegs. This doesn't increase the number of MIMG instructions.

https://github.com/llvm/llvm-project/pull/139121